Machine learning on FPGAs using HLS
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Updated
Oct 21, 2024 - C++
Machine learning on FPGAs using HLS
DaCe - Data Centric Parallel Programming
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
Real-time binocular stereo vision FPGA system with OV5640 cameras
FPGA implementation of Canny edge detection by using Vivado HLS
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
FPGA acceleration of arbitrary precision floating point computations.
A Vivado HLS Command Line Helper Tool
This project implements a convolution kernel based on vivado HLS on zcu104
Lenet for MNIST handwritten digit recognition using Vivado hls tool
[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
Real-time binocular stereo vision FPGA system with OV5640 cameras
Source codes for High Level Synthesis for Fixed Progammable Gate Arrays (FPGAs). Can be converted to RTL using Vivado HLS or SDSoC.
CPU implementation of the Image stitching using FAST. For FPGA implementation visit tharaka27-SocStitcher.
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