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Introduce RISC-V architecture support #190

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Summary of the PR

Introduce RISC-V architecture to loader, bringing #163 forward.

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  • All commits in this PR have Signed-Off-By trailers (with
    git commit -s), and the commit message has max 60 characters for the
    summary and max 75 characters for each description line.
  • All added/changed functionality has a corresponding unit/integration
    test.
  • All added/changed public-facing functionality has entries in the "Upcoming
    Release" section of CHANGELOG.md (if no such section exists, please create one).
  • Any newly added unsafe code is properly documented.

@TimePrinciple TimePrinciple changed the title Introduce riscv architecture Introduce RISC-V architecture support Sep 11, 2024
@TimePrinciple TimePrinciple marked this pull request as draft September 11, 2024 09:53
@TimePrinciple TimePrinciple force-pushed the introduce-riscv-architecture branch 4 times, most recently from 3d64381 to 8a465c5 Compare October 15, 2024 07:21
@TimePrinciple TimePrinciple marked this pull request as ready for review October 15, 2024 07:31
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@roypat @rbradford @ShadowCurse PTAL when convenient :)

endeneer and others added 7 commits October 16, 2024 17:44
Initial porting to support loading Linux PE Image on RISC-V platform.

Signed-off-by: Tan En De <ende.tan@starfivetech.com>
Refactor RISC-V loader to work with PE image.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
Introduce configurator module of riscv64. Implement `Configurator` for
riscv64 platform, add according unit-tests.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
As `rustfmt` suggested, `config` is deprecated, moving to `config.toml`.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
Add `.platform` file to enable x86_64, aarch64, riscv64 CI.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
As clippy command in our CI mandates: `cargo clippy --workspace --bins
--examples --benches --all-features --all-targets -- -D warnings -D
clippy::undocumented_unsafe_blocks`, add benchmarck test to appease
clippy.

Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
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I feel like there is a lot of code duplicated between the ARM and RISC implementations that doesn't really need to be duplicated like this. Can you have a look at that, to see where we can reuse instead? :o

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Instead of duplicating this entire benchmark, let's just rename the aarch64.rs file to something more appropriate (fdt.rs, maybe), and simply have it cfg'd with `any(target_arch = "aarch64", target_arch = "riscv64")

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This file is also a 1:1 copy of the one in the aarch64 module. Let's figure out a way to reuse these somehow

///
/// # Returns
/// * KernelLoaderResult
fn load<F, M: GuestMemory>(
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This is also very similar to the existing aarch64 code. Can we reuse part of it somehow?

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I feel like there is a lot of code duplicated between the ARM and RISC implementations that doesn't really need to be duplicated like this. Can you have a look at that, to see where we can reuse instead? :o

Yes, I noticed that, I just copied these files incase there is something to be diverged in the future

I can try to merge the common part as possible, but what should we name that, like riscs ? :o

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rbradford commented Oct 16, 2024

I feel like there is a lot of code duplicated between the ARM and RISC implementations that doesn't really need to be duplicated like this. Can you have a look at that, to see where we can reuse instead? :o

Yes, I noticed that, I just copied these files incase there is something to be diverged in the future

I can try to merge the common part as possible, but what should we name that, like riscs ? :o

Maybe move the fdt code to a higher level and then pub use to expose it from the arch module and keep the same API?

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4 participants