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Introduce RISC-V architecture support #190
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Introduce RISC-V architecture support #190
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@roypat @rbradford @ShadowCurse PTAL when convenient :) |
Initial porting to support loading Linux PE Image on RISC-V platform. Signed-off-by: Tan En De <ende.tan@starfivetech.com>
Refactor RISC-V loader to work with PE image. Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
Introduce configurator module of riscv64. Implement `Configurator` for riscv64 platform, add according unit-tests. Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
As `rustfmt` suggested, `config` is deprecated, moving to `config.toml`. Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
Add `.platform` file to enable x86_64, aarch64, riscv64 CI. Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
As clippy command in our CI mandates: `cargo clippy --workspace --bins --examples --benches --all-features --all-targets -- -D warnings -D clippy::undocumented_unsafe_blocks`, add benchmarck test to appease clippy. Signed-off-by: Ruoqing He <heruoqing@iscas.ac.cn>
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I feel like there is a lot of code duplicated between the ARM and RISC implementations that doesn't really need to be duplicated like this. Can you have a look at that, to see where we can reuse instead? :o
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Instead of duplicating this entire benchmark, let's just rename the aarch64.rs
file to something more appropriate (fdt.rs
, maybe), and simply have it cfg'd with `any(target_arch = "aarch64", target_arch = "riscv64")
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This file is also a 1:1 copy of the one in the aarch64 module. Let's figure out a way to reuse these somehow
/// | ||
/// # Returns | ||
/// * KernelLoaderResult | ||
fn load<F, M: GuestMemory>( |
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This is also very similar to the existing aarch64 code. Can we reuse part of it somehow?
Yes, I noticed that, I just copied these files incase there is something to be diverged in the future I can try to merge the common part as possible, but what should we name that, like |
Maybe move the fdt code to a higher level and then |
Summary of the PR
Introduce RISC-V architecture to
loader
, bringing #163 forward.Requirements
Before submitting your PR, please make sure you addressed the following
requirements:
git commit -s
), and the commit message has max 60 characters for thesummary and max 75 characters for each description line.
test.
Release" section of CHANGELOG.md (if no such section exists, please create one).
unsafe
code is properly documented.