CORE-V: Support Multiply Accumulate Extension #1

pietraferreira · 2023-08-14T11:21:16Z

This PR presents the comprehensive implementation of the MAC extension for CORE-V, in preparation for upstream.

I have thoroughly tested the implementation to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust.

Test results (using this toolchain):

Category	Baseline	With commit	Comparison
Expected passes	158326	158340	+21
Unexpected failures	68	75	-
Unexpected successes	3	3	-
Expected failures	899	899	-
Unresolved testcases	4	4	-
Unsupported tests	6641	6774	+133

Multilib enabled:

Category	Baseline	With commit	Comparison
Expected passes	1112504	1112651	+147
Unexpected failures	1021	1021	-
Unexpected successes	23	23	-
Expected failures	6295	6295	-
Unresolved testcases	116	116	-
Unsupported tests	44779	45710	+931

TODO: The failures + unsupported tests are due to...

TODO: Add contributors! Not adding it now so people don't keep getting notifications :) Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributos: gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Added XCVmac. * config/riscv/riscv-ftypes.def: Added XCVmac builtins. * config/riscv/riscv-opts.h: Likewise. * config/riscv/riscv.md: Likewise. * config/riscv/riscv.opt: Likewise. * doc/extend.texi: Added XCVmac builtin documentation. * config/riscv/corev.def: New file. * config/riscv/corev.md: New file. gcc/testsuite/ChangeLog: * lib/target-supports.exp: * gcc.target/riscv/cv-march-xcvmac-compile.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-mac.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-machhsn.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-machhsrn.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-machhun.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-machhurn.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-macsn.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-macsrn.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-macun.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-macurn.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-msu.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-mulhhsn.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-mulhhsrn.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-mulhhun.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-mulhhurn.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-mulsn.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-mulsrn.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-mulun.c: New test. * gcc.target/riscv/cv-march-xcvmac-fail-compile-mulurn.c: New test. * gcc.target/riscv/cv-march-xcvmac-test-autogeneration.c: New test. Signed-off-by: Mary Bennett <mary.bennett@embecosm.com>

MaryBennett · 2023-08-29T10:15:37Z

What we want the naming scheme for the testcases to be?
a. cv-march-xcv<ext>-compile-<insn>.c and cv-march-xcv<ext>-fail-compile-<insn>.c
b. cv-<ext>-<insn>-compile.c

MaryBennett · 2023-08-29T15:28:31Z

The tests should also be in GCC format, right?
eg

int
foo ()

MaryBennett · 2023-08-29T15:35:03Z

We will want the corresponding header file, too.

craigblackmore · 2023-08-29T15:14:07Z

gcc/common/config/riscv/riscv-common.cc

@@ -1462,6 +1463,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
  {"xtheadmemidx",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
  {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
  {"xtheadsync",    &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+  {"xcvmac",        &gcc_options::x_riscv_xcv_flags, MASK_XCVMAC},


Move above xtheadba to keep in alphabetical order.

craigblackmore · 2023-08-29T15:38:51Z

gcc/config/riscv/corev.md

@@ -0,0 +1,264 @@
+;; Machine description for RISC-V MAC operations.


Suggested change

;; Machine description for RISC-V MAC operations.

;; Machine description for CORE-V vendor extensions.

craigblackmore · 2023-08-29T15:39:18Z

gcc/config/riscv/corev.md

+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_insn "riscv_cv_mac_mac"


Suggested change

(define_insn "riscv_cv_mac_mac"

;; XCVMAC extension

(define_insn "riscv_cv_mac_mac"

craigblackmore · 2023-08-29T15:40:43Z

gcc/config/riscv/riscv-ftypes.def

+DEF_RISCV_FTYPE (3, (USI, USI, USI, UQI)) //RISCV_USI_FTYPE_USI_USI_UQI
+DEF_RISCV_FTYPE (3, (SI, SI, SI, UQI)) //RISCV_SI_FTYPE_SI_SI_UQI
+DEF_RISCV_FTYPE (4, (USI, USI, USI, USI, UQI)) //RISCV_USI_FTYPE_USI_USI_USI_UQI
+DEF_RISCV_FTYPE (4, (SI, SI, SI, SI, UQI)) //RISCV_SI_FTYPE_SI_SI_SI_UQI


Are these comments needed?

craigblackmore · 2023-08-29T15:41:50Z

gcc/config/riscv/riscv-opts.h

@@ -319,4 +319,8 @@ enum riscv_entity
 #define TARGET_VECTOR_VLS                                                      \
  (TARGET_VECTOR && riscv_autovec_preference == RVV_SCALABLE)

+#define MASK_XCVMAC    (1 <<  0)
+
+#define TARGET_XCVMAC    ((riscv_xcv_flags & MASK_XCVMAC) != 0)


Should these go alongside the existing vendor targets/masks?

craigblackmore · 2023-08-29T15:43:11Z

gcc/config/riscv/riscv.opt

@@ -254,6 +254,9 @@ int riscv_ztso_subext
 TargetVariable
 int riscv_xthead_subext

+TargetVariable
+int riscv_xcv_flags


Put alphabetical above riscv_xthead_subext?

craigblackmore · 2023-08-29T15:45:23Z

gcc/doc/extend.texi

@@ -21614,6 +21614,82 @@ vector intrinsic specification, which is available at the following link:
 @uref{https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/v0.11.x}.
 All of these functions are declared in the include file @file{riscv_vector.h}.

+These built-in functions are available for the CORE-V MAC machine
+architecture. For more information on CORE-V built-ins, please see
+@uref{https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-hardware-loop-builtins-xcvhwlp}


This should go in it's own subsection e.g. CORE-V Vendor Intrinsics.

URL mentions hardware-loop-builtins?

craigblackmore · 2023-08-29T15:47:18Z

gcc/testsuite/gcc.target/riscv/cv-march-xcvmac-fail-compile-mac.c

+/* { dg-options "-march=rv32i_xcvmac -mabi=ilp32" } */
+
+#include <stdint.h>
+#include<stdio.h>


Shouldn't need stdio.h for this and the other tests.

craigblackmore · 2023-08-29T15:49:21Z

gcc/testsuite/lib/target-supports.exp

+        {
+          asm ("cv.mac t0, t1, t2");
+        }
+    } "-march=rv32ixcvmac" ]


Should this be rv32i_xcvmac?

pietraferreira · 2023-08-30T13:39:11Z

What we want the naming scheme for the testcases to be? a. cv-march-xcv<ext>-compile-<insn>.c and cv-march-xcv<ext>-fail-compile-<insn>.c b. cv-<ext>-<insn>-compile.c

It would make sense to have one cv-march-xcvmac-compile-insn.c and then a cv-march-xcvmac-fail-compile-insn.c I think. The reason I didn't compile all the fail tests into one file was because some have different dg options. I don't think I'm able to specify the dg option to a function, so I'm not sure how I'd have different options for different instructions. Therefore, I kept them in their own separate files, but still thought it would be nice to have all the compile ones in a single file. Not sure if it's the right approach though, happy to hear your thoughts.

pietraferreira · 2023-08-30T13:43:01Z

We will want the corresponding header file, too.

What do you mean here? Not sure what header file you are referring to, sorry :(

MaryBennett · 2023-09-07T09:20:33Z

We will want the corresponding header file, too.

What do you mean here? Not sure what header file you are referring to, sorry :(

During the CORE-V LLVM / GCC calls, it was decided that the best way to allow the toolchain to communicate with IDEs was to add a header file of the builtins.
It's still a work in progress so I think we can skip this step.

MaryBennett · 2023-09-07T11:18:32Z

List of contributors:
Mary Bennett mary.bennett@embecosm.com
Nandni Jamnadas nandni.jamnadas@embecosm.com
Pietra Ferreira pietra.ferreira@embecosm.com
Charlie Keaney
Jessica Mills
Craig Blackmore craig.blackmore@embecosm.com
Simon Cook simon.cook@embecosm.com
Jeremy Bennett jeremy.bennett@embecosm.com
Helene Chelin helene.chelin@embecosm.com

pietraferreira force-pushed the pf-upstream-xcvmac branch 3 times, most recently from 4b02595 to fd43628 Compare August 21, 2023 09:55

pietraferreira force-pushed the pf-upstream-xcvmac branch from fd43628 to 58eaa10 Compare August 23, 2023 13:03

craigblackmore reviewed Aug 29, 2023

View reviewed changes

craigblackmore mentioned this pull request Aug 29, 2023

CORE-V: Support ALU Extension #2

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CORE-V: Support Multiply Accumulate Extension #1

CORE-V: Support Multiply Accumulate Extension #1

pietraferreira commented Aug 14, 2023 •

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MaryBennett commented Sep 7, 2023 •

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		@@ -0,0 +1,264 @@
		;; Machine description for RISC-V MAC operations.

	;; Machine description for RISC-V MAC operations.
	;; Machine description for CORE-V vendor extensions.

CORE-V: Support Multiply Accumulate Extension #1

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CORE-V: Support Multiply Accumulate Extension #1

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pietraferreira commented Aug 30, 2023

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