This is a short tabular description of the contents of each folder in the repo.
Folder | Description |
---|---|
rtl/SystemVerilog | SV RTL implementation files |
rtl/VHDL | VHDL RTL implementation files |
cocotb_sim | Functional Verification with CoCoTB (Python-based) |
pyuvm_sim | Functional Verification with pyUVM (Python impl. of UVM standard) |
verilator_sim | Functional Verification with Verilator (C++ based) |
formal | Formal Verification using PSL properties and YoysHQ/sby |
This is the tree view of the strcture of the repo.
. ├── rtl │ ├── SystemVerilog │ │ └── SV files │ └── VHDL │ └── VHD files ├── cocotb_sim │ ├── Makefile │ └── python files ├── pyuvm_sim │ ├── Makefile │ └── python files ├── verilator_sim │ ├── Makefile │ └── verilator tb └── formal ├── Makefile └── PSL properties file, scripts