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code cleaning
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xtofalex committed Oct 19, 2024
1 parent 755674e commit 33e3845
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Showing 3 changed files with 8 additions and 30 deletions.
8 changes: 4 additions & 4 deletions src/VerilogParser.yy
Original file line number Diff line number Diff line change
Expand Up @@ -214,7 +214,7 @@ constant_expression: constant_primary {
}
| unary_operator constant_primary {
auto expression = $2;
if (expression.value_.index() == naja::verilog::Expression::NUMBER) {
if (expression.value_.index() == naja::verilog::ConstantExpression::NUMBER) {
auto number = std::get<naja::verilog::Number>(expression.value_);
if ($1 == "-") { number.sign_ = false; }
$$.valid_ = true;
Expand All @@ -225,8 +225,8 @@ constant_expression: constant_primary {
}

range: '[' constant_expression ':' constant_expression ']' {
if ($2.value_.index() == naja::verilog::Expression::NUMBER and
$4.value_.index() == naja::verilog::Expression::NUMBER) {
if ($2.value_.index() == naja::verilog::ConstantExpression::NUMBER and
$4.value_.index() == naja::verilog::ConstantExpression::NUMBER) {
auto number1 = std::get<naja::verilog::Number>($2.value_);
auto number2 = std::get<naja::verilog::Number>($4.value_);
$$ = Range(number1.getInt(), number2.getInt());
Expand Down Expand Up @@ -359,7 +359,7 @@ hierarchical_identifier
//only numeric values (one bit) [4] or [4:5] are supported
constant_range_expression.opt: %empty { $$.valid_ = false; }
| '[' constant_expression ']' {
if ($2.value_.index() == naja::verilog::Expression::NUMBER) {
if ($2.value_.index() == naja::verilog::ConstantExpression::NUMBER) {
auto number = std::get<naja::verilog::Number>($2.value_);
$$ = Range(number.getInt());
} else {
Expand Down
6 changes: 3 additions & 3 deletions test/NajaVerilogTest12.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -68,7 +68,7 @@ TEST(NajaVerilogTest12, test) {
EXPECT_EQ("INIT", def0Path[1].name_);
EXPECT_FALSE(def0Path[1].escaped_);
EXPECT_EQ("2'h1", def0Value.getString());
EXPECT_EQ(Expression::Type::NUMBER ,def0Value.value_.index());
EXPECT_EQ(ConstantExpression::Type::NUMBER ,def0Value.value_.index());

auto def1Path = test->defParameterAssignments_[1].first;
auto def1Value = test->defParameterAssignments_[1].second;
Expand All @@ -77,7 +77,7 @@ TEST(NajaVerilogTest12, test) {
EXPECT_FALSE(def1Path[0].escaped_);
EXPECT_EQ("RAMINDEX", def1Path[1].name_);
EXPECT_FALSE(def1Path[1].escaped_);
EXPECT_EQ(Expression::Type::STRING ,def1Value.value_.index());
EXPECT_EQ(ConstantExpression::Type::STRING ,def1Value.value_.index());
EXPECT_EQ("mem_regfile[7:0]%32%8%SPEED%0%0%MICRO_RAM", def1Value.getString());

auto def2Path = test->defParameterAssignments_[2].first;
Expand All @@ -87,6 +87,6 @@ TEST(NajaVerilogTest12, test) {
EXPECT_TRUE(def2Path[0].escaped_);
EXPECT_EQ("INIT", def2Path[1].name_);
EXPECT_FALSE(def2Path[1].escaped_);
EXPECT_EQ(Expression::Type::NUMBER ,def2Value.value_.index());
EXPECT_EQ(ConstantExpression::Type::NUMBER ,def2Value.value_.index());
EXPECT_EQ("2'h2", def2Value.getString());
}
24 changes: 1 addition & 23 deletions test/benchmarks/test14.v
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@
<<<<<<< HEAD
/*
test attributes (pragmas)
*/
Expand Down Expand Up @@ -26,25 +25,4 @@ module adder(a, b, s);
.O(_05_[4])
);

endmodule
=======
//Testing escape identifiers

module \mod% ();
output[40:0] \asqrt ;
wire \asqrt[33] ;

//parameter \mypar^ = 32'd1; FIXME: need to support parameters

\$$MOD #(
.INIT(8'h2b)
) \ins@2 (
.I0(\busa+index ),
.I1(\-clock ),
.I2(\asqrt[33] ),
.I3(\asqrt [33]),
.Q(\{a,b} )
);

endmodule
>>>>>>> main
endmodule

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