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A VHDL implementation of the bitonic sort

This bitonic sort is based on the description given in:

The software implements the sorter using recursively generated entities using VHDL-2008. Because it targets FPGAs that allow initializing values, no reset is implemented. In other cases, a reset signal may be desired.

Note, there is also an HLS bitonic sort implementation in https://github.com/mmxsrup/bitonic-sort.

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