Repository of RISC-V architecture soft-cores written while practicing computer architecture and Verilog.
- RV32I-Single-Cycle: First core ever attempted. Simple single cycle single core implementing RV32I instruction set, with Harvard architecture.
-
Notifications
You must be signed in to change notification settings - Fork 0
jgesc/riscv-cores
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
Repository of RISC-V architecture soft-cores written while practicing computer architecture and Verilog