S-AES-Design-and-Verification-using-SystemVerilog-and-UVM

Simplified Advanced Encryption Standard (S-AES) Design and Verification Using System Verilog and UVM.

UVM Architecture

Coverage Results

• Functional Coverage:

  

• Code Coverage:

Compilation and Simulation Steps

To compile the design and testbench, use the following command:

 vlog S_AES_Package.svh S_AES_Top.sv +cover

To simulate and run test with coverage analysis, use the following command:

vsim -batch S_AES_Top -coverage -do "run -all; coverage report -codeAll -cvg -verbose"