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cx16-bank.cfg
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cx16-bank.cfg
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FEATURES {
STARTADDRESS: default = $0801;
}
SYMBOLS {
__LOADADDR__: type = import;
__EXEHDR__: type = import;
__BANKRAMADDR__: type = import;
__STACKSIZE__: type = weak, value = $0800; # 2K stack
__HIMEM__: type = weak, value = $9F00;
__BANKRAMSTART__: type = export, value = $A000;
__BANKRAMSIZE__: type = weak, value = $2000; # 8K banked RAM
}
MEMORY {
ZP: file = "", define = yes, start = $0022, size = $0080 - $0022;
LOADADDR: file = %O, start = %S - 2, size = $0002;
HEADER: file = %O, define = yes, start = %S, size = $000D;
MAIN: file = %O, define = yes, start = __HEADER_LAST__, size = __HIMEM__ - __HEADER_LAST__;
BSS: file = "", start = __ONCE_RUN__, size = __HIMEM__ - __ONCE_RUN__ - __STACKSIZE__;
BRAM01ADDR: file = "%O.01", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM01: file = "%O.01", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $01;
BRAM02ADDR: file = "%O.02", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM02: file = "%O.02", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $02;
BRAM03ADDR: file = "%O.03", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM03: file = "%O.03", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $03;
BRAM04ADDR: file = "%O.04", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM04: file = "%O.04", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $04;
BRAM05ADDR: file = "%O.05", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM05: file = "%O.05", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $05;
BRAM06ADDR: file = "%O.06", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM06: file = "%O.06", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $06;
BRAM07ADDR: file = "%O.07", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM07: file = "%O.07", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $07;
BRAM08ADDR: file = "%O.08", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM08: file = "%O.08", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $08;
BRAM09ADDR: file = "%O.09", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM09: file = "%O.09", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $09;
BRAM0AADDR: file = "%O.0A", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM0A: file = "%O.0A", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0A;
BRAM0BADDR: file = "%O.0B", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM0B: file = "%O.0B", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0B;
BRAM0CADDR: file = "%O.0C", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM0C: file = "%O.0C", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0C;
BRAM0DADDR: file = "%O.0D", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM0D: file = "%O.0D", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0D;
BRAM0EADDR: file = "%O.0E", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM0E: file = "%O.0E", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0E;
BRAM0FADDR: file = "%O.0F", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM0F: file = "%O.0F", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $0F;
BRAM10ADDR: file = "%O.10", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM10: file = "%O.10", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $10;
BRAM11ADDR: file = "%O.11", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM11: file = "%O.11", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $11;
BRAM12ADDR: file = "%O.12", start = __BANKRAMSTART__ - 2, size = $0002;
BRAM12: file = "%O.12", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $12;
BRAMDEBUGADDR: file = "%O.DEBUG", start = __BANKRAMSTART__ - 2, size = $0002;
BRAMDEBUG: file = "%O.DEBUG", start = __BANKRAMSTART__, size = __BANKRAMSIZE__, bank = $13;
}
SEGMENTS {
ZEROPAGE: load = ZP, type = zp;
EXTZP: load = ZP, type = zp, optional = yes;
LOADADDR: load = LOADADDR, type = ro;
EXEHDR: load = HEADER, type = ro;
STARTUP: load = MAIN, type = ro, optional = yes;
LOWCODE: load = MAIN, type = ro, optional = yes;
CODE: load = MAIN, type = ro;
RODATA: load = MAIN, type = ro;
DATA: load = MAIN, type = rw;
INIT: load = MAIN, type = rw, optional = yes;
ONCE: load = MAIN, type = ro, define = yes;
BSS: load = BSS, type = bss, define = yes;
BRAM01ADDR: load = BRAM01ADDR, type = ro, optional = yes;
BANKRAM01: load = BRAM01, type = rw, optional = yes, define = yes;
BRAM02ADDR: load = BRAM02ADDR, type = ro, optional = yes;
BANKRAM02: load = BRAM02, type = rw, optional = yes, define = yes;
BRAM03ADDR: load = BRAM03ADDR, type = ro, optional = yes;
BANKRAM03: load = BRAM03, type = rw, optional = yes, define = yes;
BRAM04ADDR: load = BRAM04ADDR, type = ro, optional = yes;
BANKRAM04: load = BRAM04, type = rw, optional = yes, define = yes;
BRAM05ADDR: load = BRAM05ADDR, type = ro, optional = yes;
BANKRAM05: load = BRAM05, type = rw, optional = yes, define = yes;
BRAM06ADDR: load = BRAM06ADDR, type = ro, optional = yes;
BANKRAM06: load = BRAM06, type = rw, optional = yes, define = yes;
BRAM07ADDR: load = BRAM07ADDR, type = ro, optional = yes;
BANKRAM07: load = BRAM07, type = rw, optional = yes, define = yes;
BRAM08ADDR: load = BRAM08ADDR, type = ro, optional = yes;
BANKRAM08: load = BRAM08, type = rw, optional = yes, define = yes;
BRAM09ADDR: load = BRAM09ADDR, type = ro, optional = yes;
BANKRAM09: load = BRAM09, type = rw, optional = yes, define = yes;
BRAM0AADDR: load = BRAM0AADDR, type = ro, optional = yes;
BANKRAM0A: load = BRAM0A, type = rw, optional = yes, define = yes;
BRAM0BADDR: load = BRAM0BADDR, type = ro, optional = yes;
BANKRAM0B: load = BRAM0B, type = rw, optional = yes, define = yes;
BRAM0CADDR: load = BRAM0CADDR, type = ro, optional = yes;
BANKRAM0C: load = BRAM0C, type = rw, optional = yes, define = yes;
BRAM0DADDR: load = BRAM0DADDR, type = ro, optional = yes;
BANKRAM0D: load = BRAM0D, type = rw, optional = yes, define = yes;
BRAM0EADDR: load = BRAM0EADDR, type = ro, optional = yes;
BANKRAM0E: load = BRAM0E, type = rw, optional = yes, define = yes;
BRAM0FADDR: load = BRAM0FADDR, type = ro, optional = yes;
BANKRAM0F: load = BRAM0F, type = rw, optional = yes, define = yes;
BRAM10ADDR: load = BRAM10ADDR, type = ro, optional = yes;
BANKRAM10: load = BRAM10, type = rw, optional = yes, define = yes;
BRAM11ADDR: load = BRAM11ADDR, type = ro, optional = yes;
BANKRAM11: load = BRAM11, type = rw, optional = yes, define = yes;
BRAM12ADDR: load = BRAM12ADDR, type = ro, optional = yes;
BANKRAM12: load = BRAM12, type = rw, optional = yes, define = yes;
BANKRAMDEBUGADDR: load = BRAMDEBUGADDR, type = ro, optional = yes;
BANKRAMDEBUG: load = BRAMDEBUG, type = rw, optional = yes, define = yes;
}
FEATURES {
CONDES: type = constructor,
label = __CONSTRUCTOR_TABLE__,
count = __CONSTRUCTOR_COUNT__,
segment = ONCE;
CONDES: type = destructor,
label = __DESTRUCTOR_TABLE__,
count = __DESTRUCTOR_COUNT__,
segment = RODATA;
CONDES: type = interruptor,
label = __INTERRUPTOR_TABLE__,
count = __INTERRUPTOR_COUNT__,
segment = RODATA,
import = __CALLIRQ__;
}