synopsys
Here are 36 public repositories matching this topic...
2 bit random number generation under data encryption using Synopsys Custom Compiler in 32nm CMOS Technology
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Feb 24, 2022
Mold: A Modern Linker 🦠 ARCV2 Support, Linker Script support is the aim for embedded projects
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Oct 8, 2024 - C++
Ansible Role: Polaris - Installs and configures Polaris CLI
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Aug 25, 2021
2AMD15 - Big Data Management - Prof. Papapetrou - TU/e
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Jul 3, 2023 - Python
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Jun 9, 2023 - VHDL
I2S (Inter-IC Sound) interface module with APB (Advanced Peripheral Bus) interface signals. It has control logic for writing and reading data to/from a 4x32-bit FIFO and generates clock (sck), word select (ws), and serial data (sd) signals for I2S transmission.
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Oct 8, 2024 - Verilog
Designing a Pseudo dynamic latched comparator in 28nm CMOS Technology using Synopsys Tools.
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Feb 26, 2022
Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT
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Jul 11, 2021 - Verilog
Designing JK Flip-Flop CMOS using Synopsys Custom Compiler.
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Feb 27, 2022
This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).
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May 12, 2024 - SystemVerilog
Waveform viewer for Synopsys CustomCompiler, text table format, simulation data
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Sep 22, 2022 - Python
Command completion for Synopsys (Black Duck) Detect commands
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Dec 16, 2021 - Shell
A small collection of tutorials and tools for ASIC design.
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May 16, 2017 - SystemVerilog
Implementation of a MIPS CPU using Verilog.
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May 19, 2023 - Verilog
DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino
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Jan 16, 2023 - Verilog
Synopsys Security Plugin provides functionality for performing Security Scan with Black Duck, Coverity and Polaris.
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Oct 1, 2024 - Java
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