Implementation and evaluation of Pentium_m, GShare, One_bit, Bimode & Perceptron branch predictors within the Xeon X5550 Gainestown Nehalem microarchitecture
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Updated
Jul 31, 2023 - C
Implementation and evaluation of Pentium_m, GShare, One_bit, Bimode & Perceptron branch predictors within the Xeon X5550 Gainestown Nehalem microarchitecture
C++ based implementation of the VPC indirect branch prediction algorithm.
Branch prediction using branch correlations. Made as part of the course Data-driven Program Analysis (CS686)
Simulation of a bimodal two-level single branch/jump predictor, implemented in Python, for High Performance Processors (2022-23).
VHDL code of three branch predictors
Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.
C++ Macro definitions for easy branch hinting.
Computer Architecture Assignments (HY425) [winter semester of 2023].
The WIOM: A RV32IM In-Order pipelined cpu with no cache and a naive branch predictor.
同济大学CS《计算机系统实验》实验一TongJi University CS computer system experiment assignment 1
Educational project aimed at evaluating the effectiveness of different correlating branch predictors on benchmarks
This repository contains code for various branch predictors. These were written as part of a classroom exercise for the CS810: Advanced Computer Architecture course at IIT Dharwad.
Spectre attack variant 1 is used here to extract an image data buffer from a program. The output image data is then decoded and median filters are applied to remove the hot pixels in the output image. Here I have included files for RGB and base64 format.
MIPT-V Pipeline Flowchart Visualizer
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