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Bootloader.qsf
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Bootloader.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
# Date created = 16:08:58 November 09, 2010
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Bootloader_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE55F23C8
set_global_assignment -name TOP_LEVEL_ENTITY Bootloader
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:08:58 NOVEMBER 09, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Standard Edition"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_instance_assignment -name CLOCK_SETTINGS IF_clk -to IF_clk
set_instance_assignment -name CLOCK_SETTINGS Tx_clock_2 -to Tx_clock_2
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS64
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY build
set_location_assignment PIN_AA11 -to INA_CLK
set_location_assignment PIN_B12 -to PHY_CLK125
set_location_assignment PIN_C13 -to PHY_MDC
set_location_assignment PIN_B13 -to PHY_MDIO
set_location_assignment PIN_B14 -to PHY_RESET_N
set_location_assignment PIN_B8 -to PHY_RX[3]
set_location_assignment PIN_A9 -to PHY_RX[2]
set_location_assignment PIN_B9 -to PHY_RX[1]
set_location_assignment PIN_A10 -to PHY_RX[0]
set_location_assignment PIN_B11 -to PHY_RX_CLOCK
set_location_assignment PIN_A7 -to PHY_TX[3]
set_location_assignment PIN_B6 -to PHY_TX[2]
set_location_assignment PIN_A6 -to PHY_TX[1]
set_location_assignment PIN_B5 -to PHY_TX[0]
set_location_assignment PIN_E5 -to PHY_TX_CLOCK
set_location_assignment PIN_A8 -to PHY_TX_EN
set_location_assignment PIN_B10 -to PHY_RX_DV
set_location_assignment PIN_A3 -to ECS
set_location_assignment PIN_A4 -to ESCK
set_location_assignment PIN_B4 -to ESI
set_location_assignment PIN_B3 -to ESO
set_location_assignment PIN_H21 -to KEY_DASH
set_location_assignment PIN_H22 -to KEY_DOT
set_location_assignment PIN_H1 -to NCONFIG
set_location_assignment PIN_F1 -to led1
set_location_assignment PIN_E1 -to led2
set_location_assignment PIN_C1 -to led3
set_location_assignment PIN_B1 -to led4
set_instance_assignment -name IO_STANDARD "1.8 V" -to INA_CLK
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_P1 -to FPGA_PTT
set_location_assignment PIN_P2 -to PTT_2
set_location_assignment PIN_M2 -to UO0
set_location_assignment PIN_V1 -to UO1
set_location_assignment PIN_U1 -to UO2
set_location_assignment PIN_R1 -to UO3
set_location_assignment PIN_U2 -to UO4
set_location_assignment PIN_R2 -to UO5
set_location_assignment PIN_N1 -to UO6
set_location_assignment PIN_V2 -to ANT
set_location_assignment PIN_N2 -to TUNE
set_location_assignment PIN_M1 -to VNA
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_location_assignment PIN_J1 -to test1
set_location_assignment PIN_H2 -to test2
set_instance_assignment -name FAST_INPUT_REGISTER ON -to PHY_RX_DV
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to PHY_TX[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to PHY_TX[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to PHY_TX[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to PHY_TX[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to PHY_TX_CLOCK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to PHY_TX_EN
set_instance_assignment -name FAST_INPUT_REGISTER ON -to PHY_RX[3]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to PHY_RX[2]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to PHY_RX[1]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to PHY_RX[0]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to PHY_RX[3]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to PHY_RX[2]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to PHY_RX[1]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to PHY_RX[0]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to PHY_RX_DV
set_instance_assignment -name GLOBAL_SIGNAL OFF -to PHY_TX[3]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to PHY_TX[2]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to PHY_TX[1]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to PHY_TX[0]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to PHY_TX_CLOCK
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_location_assignment PIN_K1 -to DATAIN
set_location_assignment PIN_K2 -to DCLK
set_location_assignment PIN_D1 -to DATAOUT
set_location_assignment PIN_E2 -to FLASH_NCE
set_location_assignment PIN_L22 -to MCU_UART_RX
set_location_assignment PIN_L21 -to MCU_UART_TX
set_location_assignment PIN_J22 -to MCU_NOT_CON -disable
set_location_assignment PIN_K21 -to MCU_NOT_USED -disable
set_global_assignment -name VERILOG_FILE uart.v
set_global_assignment -name VERILOG_FILE Remote.v
set_global_assignment -name QIP_FILE Remote.qip
set_global_assignment -name VERILOG_FILE EEPROM.v
set_global_assignment -name VERILOG_FILE Bootloader.v
set_global_assignment -name VERILOG_FILE CRC32.v
set_global_assignment -name VERILOG_FILE Led_control.v
set_global_assignment -name VERILOG_FILE Led_flash.v
set_global_assignment -name VERILOG_FILE MDIO.v
set_global_assignment -name VERILOG_FILE Reconfigure.v
set_global_assignment -name QIP_FILE C122_PLL.qip
set_global_assignment -name QIP_FILE C125_PLL.qip
set_global_assignment -name VERILOG_FILE phy_cfg.v
set_global_assignment -name QIP_FILE ddio_in.qip
set_global_assignment -name QIP_FILE ddio_out.qip
set_global_assignment -name VERILOG_FILE Flash.v
set_global_assignment -name VERILOG_FILE mcu.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top