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AND, OR, NAND, and NOR, XOR gates with LED.circ
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AND, OR, NAND, and NOR, XOR gates with LED.circ
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="2.7.1" version="1.0">
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
<lib desc="#Wiring" name="0"/>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4">
<tool name="ROM">
<a name="contents">addr/data: 8 8
0
</a>
</tool>
</lib>
<lib desc="#I/O" name="5"/>
<lib desc="#Base" name="6">
<tool name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
</lib>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="6" map="Button2" name="Menu Tool"/>
<tool lib="6" map="Button3" name="Menu Tool"/>
<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="6" name="Poke Tool"/>
<tool lib="6" name="Edit Tool"/>
<tool lib="6" name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
<sep/>
<tool lib="0" name="Pin">
<a name="tristate" val="false"/>
</tool>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</tool>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
</toolbar>
<circuit name="main">
<a name="circuit" val="main"/>
<a name="clabel" val=""/>
<a name="clabelup" val="east"/>
<a name="clabelfont" val="SansSerif plain 12"/>
<wire from="(480,190)" to="(540,190)"/>
<wire from="(710,210)" to="(760,210)"/>
<wire from="(710,170)" to="(760,170)"/>
<wire from="(710,320)" to="(760,320)"/>
<wire from="(710,360)" to="(760,360)"/>
<wire from="(530,520)" to="(580,520)"/>
<wire from="(530,480)" to="(580,480)"/>
<wire from="(820,340)" to="(880,340)"/>
<wire from="(370,210)" to="(420,210)"/>
<wire from="(370,170)" to="(420,170)"/>
<wire from="(370,360)" to="(420,360)"/>
<wire from="(370,320)" to="(420,320)"/>
<wire from="(420,170)" to="(420,180)"/>
<wire from="(640,500)" to="(700,500)"/>
<wire from="(810,190)" to="(880,190)"/>
<wire from="(880,190)" to="(890,190)"/>
<wire from="(880,340)" to="(890,340)"/>
<wire from="(700,500)" to="(710,500)"/>
<wire from="(470,340)" to="(540,340)"/>
<wire from="(540,190)" to="(550,190)"/>
<wire from="(540,340)" to="(550,340)"/>
<comp lib="1" loc="(640,500)" name="NOR Gate"/>
<comp lib="0" loc="(530,520)" name="Pin">
<a name="tristate" val="false"/>
<a name="label" val="S1-2"/>
</comp>
<comp lib="5" loc="(700,500)" name="LED"/>
<comp lib="0" loc="(530,480)" name="Pin">
<a name="tristate" val="false"/>
<a name="label" val="S1-1"/>
</comp>
<comp lib="0" loc="(710,210)" name="Pin">
<a name="tristate" val="false"/>
<a name="label" val="S1-2"/>
</comp>
<comp lib="0" loc="(710,360)" name="Pin">
<a name="tristate" val="false"/>
<a name="label" val="S1-2"/>
</comp>
<comp lib="1" loc="(470,340)" name="AND Gate"/>
<comp lib="0" loc="(370,360)" name="Pin">
<a name="tristate" val="false"/>
<a name="label" val="S1-2"/>
</comp>
<comp lib="0" loc="(370,170)" name="Pin">
<a name="tristate" val="false"/>
<a name="label" val="S1-1"/>
</comp>
<comp lib="5" loc="(540,190)" name="LED"/>
<comp lib="0" loc="(370,320)" name="Pin">
<a name="tristate" val="false"/>
<a name="label" val="S1-1"/>
</comp>
<comp lib="5" loc="(880,190)" name="LED"/>
<comp lib="5" loc="(540,340)" name="LED"/>
<comp lib="1" loc="(480,190)" name="NAND Gate"/>
<comp lib="0" loc="(710,170)" name="Pin">
<a name="tristate" val="false"/>
<a name="label" val="S1-1"/>
</comp>
<comp lib="5" loc="(880,340)" name="LED"/>
<comp lib="1" loc="(810,190)" name="OR Gate"/>
<comp lib="0" loc="(710,320)" name="Pin">
<a name="tristate" val="false"/>
<a name="label" val="S1-1"/>
</comp>
<comp lib="1" loc="(820,340)" name="XOR Gate"/>
<comp lib="0" loc="(370,210)" name="Pin">
<a name="tristate" val="false"/>
<a name="label" val="S1-2"/>
</comp>
</circuit>
</project>