From ad88817716f887eea9a3f2edb9c8dff1b97d6510 Mon Sep 17 00:00:00 2001 From: xtof Date: Tue, 7 Nov 2023 20:18:38 +0100 Subject: [PATCH] some fixes --- README.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 63bf5fe..a840fac 100644 --- a/README.md +++ b/README.md @@ -207,7 +207,7 @@ void addAssign(const Identifiers& identifiers, const Expression& expression) is called for each assign statement, facilitating the capture of signal assignments. -In Following verilog snippets, the corresponding constructed data stuctures are detailed in pseudo C++ code. +Below are Verilog examples followed by pseudo C++ representations of the data structures that might be constructed by this callback. ```verilog assign n0 = n1; @@ -344,6 +344,8 @@ mod1 inst4(net4[7:10], {net0, net1, net2, net3}); void addParameterAssignment(const std::string& parameterName, const Expression& expression); ``` +This callback function is designed to handle parameter assignments within module instantiations. + ```verilog module test(); mod #(