diff --git a/src/VerilogTypes.h b/src/VerilogTypes.h index a0e87ae..b7bcb4c 100644 --- a/src/VerilogTypes.h +++ b/src/VerilogTypes.h @@ -252,15 +252,15 @@ struct ConstantExpression { struct Attribute { Attribute() = default; Attribute(const Attribute&) = default; - Attribute(const std::string& name, const ConstantExpression& expression): + Attribute(const naja::verilog::Identifier& name, const ConstantExpression& expression): name_(name), expression_(expression) {} std::string getString() const; std::string getDescription() const; - std::string name_ {}; - ConstantExpression expression_ {}; + naja::verilog::Identifier name_ {}; + ConstantExpression expression_ {}; }; }} // namespace verilog // namespace naja diff --git a/test/NajaVerilogTest14.cpp b/test/NajaVerilogTest14.cpp index 36ccc78..d775fb1 100644 --- a/test/NajaVerilogTest14.cpp +++ b/test/NajaVerilogTest14.cpp @@ -1,8 +1,4 @@ -<<<<<<< HEAD -// SPDX-FileCopyrightText: 2024 The Naja verilog authors -======= // SPDX-FileCopyrightText: 2024 The Naja verilog authors ->>>>>>> main // // SPDX-License-Identifier: Apache-2.0 @@ -21,89 +17,17 @@ using namespace naja::verilog; #define NAJA_VERILOG_BENCHMARKS "Undefined" #endif -TEST(NajaVerilogTest8, test) { +TEST(NajaVerilogTest14, test) { VerilogConstructorTest constructor; - std::filesystem::path test8Path( + std::filesystem::path test14Path( std::filesystem::path(NAJA_VERILOG_BENCHMARKS) / std::filesystem::path("benchmarks") - / std::filesystem::path("test8.v")); -<<<<<<< HEAD - constructor.parse(test8Path); + / std::filesystem::path("test14.v")); + constructor.parse(test14Path); ASSERT_EQ(1, constructor.modules_.size()); auto adder = constructor.modules_[0]; - EXPECT_EQ("adder", adder->name_); + EXPECT_EQ("adder", adder->identifier_.getString()); constructor.setFirstPass(false); - constructor.parse(test8Path); - -#if 0 - ASSERT_EQ(1, constructor.modules_[0]->instances_.size()); - auto instance = constructor.modules_[0]->instances_[0]; - EXPECT_EQ("ins", instance.name_); - EXPECT_EQ("mod", instance.model_); - ASSERT_EQ(3, instance.parameterAssignments_.size()); - auto paramIt = instance.parameterAssignments_.find("PARAM0"); - ASSERT_TRUE(paramIt != instance.parameterAssignments_.end()); - EXPECT_TRUE(paramIt->second.empty()); - paramIt = instance.parameterAssignments_.find("PARAM1"); - ASSERT_TRUE(paramIt != instance.parameterAssignments_.end()); - EXPECT_EQ("A", paramIt->second); - paramIt = instance.parameterAssignments_.find("PARAM2"); - ASSERT_TRUE(paramIt != instance.parameterAssignments_.end()); - EXPECT_EQ("VALUE", paramIt->second); -#endif -} -======= - - constructor.setFirstPass(true); - constructor.parse(test8Path); - ASSERT_EQ(1, constructor.modules_.size()); - auto test = constructor.modules_[0]; - EXPECT_EQ(naja::verilog::Identifier("mod%", true), test->identifier_); - EXPECT_TRUE(constructor.modules_[0]->instances_.empty()); - EXPECT_TRUE(constructor.modules_[0]->nets_.empty()); - EXPECT_TRUE(constructor.modules_[0]->assigns_.empty()); - ASSERT_EQ(1, constructor.modules_[0]->ports_.size()); - EXPECT_EQ(naja::verilog::Identifier("asqrt", true), constructor.modules_[0]->ports_[0].identifier_); - EXPECT_EQ(naja::verilog::Port::Direction::Output, constructor.modules_[0]->ports_[0].direction_); - EXPECT_TRUE(constructor.modules_[0]->ports_[0].isBus()); - EXPECT_EQ(naja::verilog::Range(40, 0), constructor.modules_[0]->ports_[0].range_); - - constructor.setFirstPass(false); - constructor.parse(test8Path); - ASSERT_EQ(1, constructor.modules_.size()); - ASSERT_EQ(1, constructor.modules_[0]->instances_.size()); - auto instance = constructor.modules_[0]->instances_[0]; - EXPECT_EQ("ins@2", instance.identifier_.name_); - EXPECT_EQ("$$MOD", instance.model_.name_); - EXPECT_TRUE(instance.orderedConnections_.empty()); - ASSERT_EQ(5, instance.connections_.size()); - EXPECT_EQ(naja::verilog::Identifier("I0", false), instance.connections_[0].port_); - EXPECT_EQ(naja::verilog::Identifier("I1", false), instance.connections_[1].port_); - EXPECT_EQ(naja::verilog::Identifier("I2", false), instance.connections_[2].port_); - EXPECT_EQ(naja::verilog::Identifier("I3", false), instance.connections_[3].port_); - EXPECT_EQ(naja::verilog::Identifier("Q", false), instance.connections_[4].port_); - EXPECT_EQ(naja::verilog::Expression::Type::RANGEIDENTIFIER, instance.connections_[0].expression_.value_.index()); - auto identifier = - std::get(instance.connections_[0].expression_.value_); - EXPECT_EQ(naja::verilog::Identifier("busa+index", true), identifier.identifier_); - EXPECT_FALSE(identifier.range_.valid_); - identifier = - std::get(instance.connections_[1].expression_.value_); - EXPECT_EQ(naja::verilog::Identifier("-clock", true), identifier.identifier_); - EXPECT_FALSE(identifier.range_.valid_); - identifier = - std::get(instance.connections_[2].expression_.value_); - EXPECT_EQ(naja::verilog::Identifier("asqrt[33]", true), identifier.identifier_); - EXPECT_FALSE(identifier.range_.valid_); - identifier = - std::get(instance.connections_[3].expression_.value_); - EXPECT_EQ(naja::verilog::Identifier("asqrt", true), identifier.identifier_); - EXPECT_TRUE(identifier.range_.valid_); - EXPECT_EQ(naja::verilog::Range(33), identifier.range_); - identifier = - std::get(instance.connections_[4].expression_.value_); - EXPECT_EQ(naja::verilog::Identifier("{a,b}", true), identifier.identifier_); - EXPECT_FALSE(identifier.range_.valid_); -} ->>>>>>> main + constructor.parse(test14Path); +} \ No newline at end of file diff --git a/test/VerilogConstructorTest.cpp b/test/VerilogConstructorTest.cpp index a381048..2d405d2 100644 --- a/test/VerilogConstructorTest.cpp +++ b/test/VerilogConstructorTest.cpp @@ -126,7 +126,7 @@ void VerilogConstructorTest::addAssign( void VerilogConstructorTest::addDefParameterAssignment( const naja::verilog::Identifiers& hierarchicalParameter, - const naja::verilog::Expression& expression) { + const naja::verilog::ConstantExpression& expression) { if (not inFirstPass()) { currentModule_->defParameterAssignments_.push_back( VerilogConstructorTest::Module::DefParameterAssignment(hierarchicalParameter, expression)); @@ -134,7 +134,7 @@ void VerilogConstructorTest::addDefParameterAssignment( } void VerilogConstructorTest::addAttribute( - const std::string& attributeName, + const naja::verilog::Identifier& attributeName, const naja::verilog::ConstantExpression& expression) { attributes_.push_back(naja::verilog::Attribute(attributeName, expression)); } \ No newline at end of file diff --git a/test/VerilogConstructorTest.h b/test/VerilogConstructorTest.h index b25cf82..6c35a42 100644 --- a/test/VerilogConstructorTest.h +++ b/test/VerilogConstructorTest.h @@ -37,11 +37,10 @@ class VerilogConstructorTest: public naja::verilog::VerilogConstructor { const naja::verilog::Expression& expression) override; virtual void addDefParameterAssignment( const naja::verilog::Identifiers& hierarchicalParameter, - const naja::verilog::Expression& expression) override; + const naja::verilog::ConstantExpression& expression) override; void addAttribute( - const std::string& attributeName, + const naja::verilog::Identifier& attributeName, const naja::verilog::ConstantExpression& expression) override; - struct OrderedInstanceConnection { OrderedInstanceConnection() = default; OrderedInstanceConnection(const OrderedInstanceConnection&) = default; @@ -124,7 +123,7 @@ class VerilogConstructorTest: public naja::verilog::VerilogConstructor { using Nets = std::vector; using Instances = std::vector; using Assigns = std::vector; - using DefParameterAssignment = std::pair; + using DefParameterAssignment = std::pair; using DefParameterAssignments = std::vector; naja::verilog::Identifier identifier_ {}; Ports ports_ {};