From 60e79b17752564e5b6b09e9297d2c23e3d9050fe Mon Sep 17 00:00:00 2001 From: xtof Date: Thu, 6 Jul 2023 21:31:52 +0200 Subject: [PATCH] Ordered Instance Connection support --- src/VerilogConstructor.h | 1 + src/VerilogParser.yy | 23 ++++++++++++++---- test/NajaVerilogTest3.cpp | 42 ++++++++++++++++++++++++++++++++- test/VerilogConstructorTest.cpp | 13 +++++++++- test/VerilogConstructorTest.h | 27 +++++++++++++++++++++ test/benchmarks/test3.v | 2 ++ 6 files changed, 101 insertions(+), 7 deletions(-) diff --git a/src/VerilogConstructor.h b/src/VerilogConstructor.h index 9240ae4..cafdd12 100644 --- a/src/VerilogConstructor.h +++ b/src/VerilogConstructor.h @@ -73,6 +73,7 @@ class VerilogConstructor { virtual void startInstantiation(const std::string& modelName) {} virtual void addInstance(const std::string& instanceName) {} virtual void addInstanceConnection(const std::string& portName, const Expression& expression) {} + virtual void addOrderedInstanceConnection(size_t portIndex, const Expression& expression) {} virtual void endInstantiation() {} virtual void addParameterAssignment(const std::string& parameterName, const Expression& expression) {} virtual void endModule() {} diff --git a/src/VerilogParser.yy b/src/VerilogParser.yy index 03e19f5..b02155c 100644 --- a/src/VerilogParser.yy +++ b/src/VerilogParser.yy @@ -66,6 +66,8 @@ #undef yylex #define yylex scanner.yylex +size_t portIndex = 0; + } %define api.value.type variant @@ -227,8 +229,10 @@ net_type | WIRE_KW { $$ = naja::verilog::Net::Type::Wire; } ; -list_of_module_instances: module_instance -| list_of_module_instances ',' module_instance; +list_of_module_instances +: module_instance +| list_of_module_instances ',' module_instance +; number : CONSTVAL_TK BASE_TK BASED_CONSTVAL_TK { @@ -302,9 +306,15 @@ expression: primary { $$ = $1; } expression.opt: %empty { $$.valid_ = false; } | expression { $$ = $1; } -ordered_port_connection: expression; +ordered_port_connection: expression { + constructor->setCurrentLocation(@$.begin.line, @$.begin.column); + constructor->addOrderedInstanceConnection(portIndex++, $1); +} -list_of_ordered_port_connections: ordered_port_connection | list_of_ordered_port_connections ',' ordered_port_connection; +list_of_ordered_port_connections +: ordered_port_connection +| list_of_ordered_port_connections ',' ordered_port_connection +; port_identifier: identifier; @@ -315,7 +325,10 @@ named_port_connection: '.' port_identifier '(' expression.opt ')' { list_of_named_port_connections: named_port_connection | list_of_named_port_connections ',' named_port_connection; -list_of_port_connections: list_of_ordered_port_connections | list_of_named_port_connections; +list_of_port_connections +: { portIndex = 0; } list_of_ordered_port_connections +| list_of_named_port_connections +; list_of_port_connections.opt: %empty | list_of_port_connections; diff --git a/test/NajaVerilogTest3.cpp b/test/NajaVerilogTest3.cpp index adf1cbd..0b20f22 100644 --- a/test/NajaVerilogTest3.cpp +++ b/test/NajaVerilogTest3.cpp @@ -105,7 +105,7 @@ TEST(NajaVerilogTest3, test0) { EXPECT_EQ(-2, test->nets_[5].range_.msb_); EXPECT_EQ(1, test->nets_[5].range_.lsb_); - ASSERT_EQ(4, test->instances_.size()); + ASSERT_EQ(6, test->instances_.size()); EXPECT_EQ("mod0", test->instances_[0].model_); EXPECT_EQ("inst0", test->instances_[0].name_); EXPECT_EQ("mod0", test->instances_[1].model_); @@ -114,6 +114,10 @@ TEST(NajaVerilogTest3, test0) { EXPECT_EQ("inst2", test->instances_[2].name_); EXPECT_EQ("mod1", test->instances_[3].model_); EXPECT_EQ("inst3", test->instances_[3].name_); + EXPECT_EQ("mod1", test->instances_[4].model_); + EXPECT_EQ("inst4", test->instances_[4].name_); + EXPECT_EQ("mod1", test->instances_[5].model_); + EXPECT_EQ("inst5", test->instances_[5].name_); auto inst0 = test->instances_[0]; ASSERT_EQ(2, inst0.connections_.size()); @@ -214,5 +218,41 @@ TEST(NajaVerilogTest3, test0) { EXPECT_EQ("net5", identifier.name_); EXPECT_TRUE(identifier.range_.singleValue_); EXPECT_EQ(-2, identifier.range_.msb_); + + auto inst4 = test->instances_[4]; + ASSERT_EQ(2, inst4.orderedConnections_.size()); + EXPECT_EQ(0, inst4.orderedConnections_[0].portIndex_); + ASSERT_TRUE(inst4.orderedConnections_[0].expression_.valid_); + EXPECT_EQ(naja::verilog::Expression::Type::IDENTIFIER, + inst4.orderedConnections_[0].expression_.value_.index()); + identifier = + std::get(inst4.orderedConnections_[0].expression_.value_); + EXPECT_TRUE(identifier.range_.valid_); + EXPECT_EQ("net4", identifier.name_); + EXPECT_FALSE(identifier.range_.singleValue_); + EXPECT_EQ(7, identifier.range_.msb_); + EXPECT_EQ(10, identifier.range_.lsb_); + + EXPECT_EQ(1, inst4.orderedConnections_[1].portIndex_); + ASSERT_TRUE(inst4.orderedConnections_[1].expression_.valid_); + EXPECT_EQ(naja::verilog::Expression::Type::CONCATENATION, + inst4.orderedConnections_[1].expression_.value_.index()); + concatenation = + std::get(inst4.orderedConnections_[1].expression_.value_); + ASSERT_EQ(4, concatenation.expressions_.size()); + + auto inst5 = test->instances_[5]; + ASSERT_EQ(1, inst5.orderedConnections_.size()); + EXPECT_EQ(0, inst5.orderedConnections_[0].portIndex_); + ASSERT_TRUE(inst5.orderedConnections_[0].expression_.valid_); + EXPECT_EQ(naja::verilog::Expression::Type::IDENTIFIER, + inst5.orderedConnections_[0].expression_.value_.index()); + identifier = + std::get(inst5.orderedConnections_[0].expression_.value_); + EXPECT_TRUE(identifier.range_.valid_); + EXPECT_EQ("net4", identifier.name_); + EXPECT_FALSE(identifier.range_.singleValue_); + EXPECT_EQ(7, identifier.range_.msb_); + EXPECT_EQ(10, identifier.range_.lsb_); } } \ No newline at end of file diff --git a/test/VerilogConstructorTest.cpp b/test/VerilogConstructorTest.cpp index 7e0e471..a30ad7f 100644 --- a/test/VerilogConstructorTest.cpp +++ b/test/VerilogConstructorTest.cpp @@ -90,6 +90,17 @@ void VerilogConstructorTest::addInstanceConnection( } } +void VerilogConstructorTest::addOrderedInstanceConnection( + size_t portIndex, + const naja::verilog::Expression& expression) { + if (not inFirstPass()) { + std::cerr << "Add ordered instance connection: " + << portIndex << " " << expression.getString() << std::endl; + Instance& instance = currentModule_->instances_.back(); + instance.orderedConnections_.push_back(OrderedInstanceConnection(portIndex, expression)); + } +} + void VerilogConstructorTest::addParameterAssignment( const std::string& parameterName, const naja::verilog::Expression& expression) { @@ -106,4 +117,4 @@ void VerilogConstructorTest::addAssign( if (not inFirstPass()) { currentModule_->assigns_.push_back(Assign(identifiers, expression)); } -} \ No newline at end of file +} diff --git a/test/VerilogConstructorTest.h b/test/VerilogConstructorTest.h index 3d567c2..7bcb204 100644 --- a/test/VerilogConstructorTest.h +++ b/test/VerilogConstructorTest.h @@ -20,6 +20,9 @@ class VerilogConstructorTest: public naja::verilog::VerilogConstructor { void addInstanceConnection( const std::string& portName, const naja::verilog::Expression& expression) override; + void addOrderedInstanceConnection( + size_t portIndex, + const naja::verilog::Expression& expression) override; void addParameterAssignment( const std::string& parameterName, const naja::verilog::Expression& expression) override; @@ -29,6 +32,28 @@ class VerilogConstructorTest: public naja::verilog::VerilogConstructor { const naja::verilog::Identifiers& identifiers, const naja::verilog::Expression& expression) override; + + struct OrderedInstanceConnection { + OrderedInstanceConnection() = default; + OrderedInstanceConnection(const OrderedInstanceConnection&) = default; + OrderedInstanceConnection( + const size_t portIndex, + const naja::verilog::Expression& expression): + portIndex_(portIndex), + expression_(expression) + {} + + std::string getString() const { + std::ostringstream stream; + stream << "OrderedInstanceConnection - port: " + << portIndex_ << " : " << expression_.getString(); + return stream.str(); + } + + size_t portIndex_ {0}; + naja::verilog::Expression expression_ {}; + }; + struct InstanceConnection { InstanceConnection() = default; InstanceConnection(const InstanceConnection&) = default; @@ -52,6 +77,7 @@ class VerilogConstructorTest: public naja::verilog::VerilogConstructor { struct Instance { using Connections = std::vector; + using OrderedConnections = std::vector; using ParameterAssignments = std::map; Instance() = default; Instance(const Instance&) = default; @@ -69,6 +95,7 @@ class VerilogConstructorTest: public naja::verilog::VerilogConstructor { std::string name_ {}; ParameterAssignments parameterAssignments_ {}; Connections connections_ {}; + OrderedConnections orderedConnections_ {}; }; struct Assign { diff --git a/test/benchmarks/test3.v b/test/benchmarks/test3.v index 838e319..672ab1b 100644 --- a/test/benchmarks/test3.v +++ b/test/benchmarks/test3.v @@ -21,5 +21,7 @@ module test(input i, output o, inout io); mod0 inst1(.i0(net4[21]), .o0(net4[5])); mod1 inst2(.i0(net4[3:6]), .o0(net5)); mod1 inst3(.i0({net0, net1, net2, net5[-2]}), .o0(net5)); + mod1 inst4(net4[7:10], {net0, net1, net2, net3}); + mod1 inst5(net4[7:10]); //only first port is connected endmodule \ No newline at end of file