From 6675a57bf697189b22cdbac7936052a7389678c2 Mon Sep 17 00:00:00 2001
From: Enzo Evers <enzoevers@gmail.com>
Date: Mon, 13 May 2024 20:58:15 +0200
Subject: [PATCH 1/2] feat: reset on flash

---
 Scripts/Stm32/Stm32f303xc/StLinkFlash.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Scripts/Stm32/Stm32f303xc/StLinkFlash.sh b/Scripts/Stm32/Stm32f303xc/StLinkFlash.sh
index 1e58fd4..7558aa5 100755
--- a/Scripts/Stm32/Stm32f303xc/StLinkFlash.sh
+++ b/Scripts/Stm32/Stm32f303xc/StLinkFlash.sh
@@ -15,4 +15,4 @@ ValidateFileExists ${BINARY_PATH}
 
 WRITE_ADDRESS=0x8000000
 
-st-flash write ${BINARY_PATH} ${WRITE_ADDRESS}
\ No newline at end of file
+st-flash --reset write ${BINARY_PATH} ${WRITE_ADDRESS}

From f0cfb5d0d171df5c2d9c0a6720541f836819dd82 Mon Sep 17 00:00:00 2001
From: Enzo Evers <enzoevers@gmail.com>
Date: Mon, 13 May 2024 20:58:31 +0200
Subject: [PATCH 2/2] feat: configure PLL

---
 .../src/SetupHardwareStm32f303xc.cpp          | 34 +++++++++++++++++--
 Code/main.cpp                                 |  3 +-
 2 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/Code/HardwareSetup/stm32/Stm32f303xc/src/SetupHardwareStm32f303xc.cpp b/Code/HardwareSetup/stm32/Stm32f303xc/src/SetupHardwareStm32f303xc.cpp
index 7d89019..ebb700f 100644
--- a/Code/HardwareSetup/stm32/Stm32f303xc/src/SetupHardwareStm32f303xc.cpp
+++ b/Code/HardwareSetup/stm32/Stm32f303xc/src/SetupHardwareStm32f303xc.cpp
@@ -41,9 +41,37 @@ static auto SetupClock() -> void {
     // HLCK - SYSCLK not divided
     RCC->CFGR &= ~RCC_CFGR_HPRE_3;
 
-    // Select HSI for SYSCLOCK
-    RCC->CFGR &= ~RCC_CFGR_SW_0;
-    RCC->CFGR &= ~RCC_CFGR_SW_1;
+    //----------
+    // PLL
+    //----------
+
+    // Stop PLL
+    RCC->CR &= ~RCC_CR_PLLON;
+    while (RCC->CR & RCC_CR_PLLRDY) {
+    }
+
+    // Use HSI/2 as the PLL source clock
+    RCC->CFGR |= RCC_CFGR_PLLSRC_HSI_DIV2;
+
+    // Max allowed frequency is 72MHz.
+    // With a PLL input frequency of 4MHz (HSI/2 = 8MHz / 2 = 4MHz)
+    // the max multiplication is 72 / 4 = 18
+
+    // PLL multiplication
+    // SYSCLOCK = 4MHz * 10 = 40MHz
+    RCC->CFGR |= RCC_CFGR_PLLMUL10;
+
+    // Enable PLL
+    RCC->CR |= RCC_CR_PLLON;
+    while (!(RCC->CR & RCC_CR_PLLRDY)) {
+    }
+
+    //----------
+    // Main clock
+    //----------
+
+    // Select PLL for SYSCLOCK
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
 
     // Enable HSI clock
     RCC->CR |= RCC_CR_HSION;
diff --git a/Code/main.cpp b/Code/main.cpp
index 86c43b5..2cc5e7e 100644
--- a/Code/main.cpp
+++ b/Code/main.cpp
@@ -42,7 +42,7 @@ int main() {
         latch.SetupConfiguration({&GPIOD->ODR, GPIO_ODR_14});
         ledOE.SetupConfiguration({&GPIOD->ODR, GPIO_ODR_15});
     }
-    uint32_t tim3Hertz = 8000000;
+    uint32_t tim3Hertz = 40000000;
     auto mainDelay = DelayStm32();
     mainDelay.SetupConfiguration({&TIM3->SR, &TIM3->ARR, &TIM3->CR1, &TIM3->PSC, tim3Hertz, TIM_SR_UIF, TIM_CR1_CEN});
 #endif
@@ -70,7 +70,6 @@ int main() {
 
     auto mainDelay = DelayDesktop();
 #endif
-
     HanoverOL037A_GPIOInterface hanoverOL037A_GPIOInterface{&clk, &clkEn, &clkSelEn, &data, &latch, &ledOE};
 
     auto hanoverOL037A = HanoverOL037A();