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madDisAsm.pas
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madDisAsm.pas
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// ***************************************************************
// madDisAsm.pas version: 2.1d · date: 2006-09-11
// -------------------------------------------------------------
// mini mini x86 disassembler
// -------------------------------------------------------------
// Copyright (C) 1999 - 2006 www.madshi.net, All Rights Reserved
// ***************************************************************
// 2006-09-11 2.1d (1) another little bug in ParseFunction fixed
// (2) several little bugs in cleartext disasm fixed
// (3) support for SSE3 added
// (4) limited support for 64bit modules added
// (5) some preparation for 64bit disassembling
// (6) minimal debug info only: function names were missing
// 2005-06-19 2.1c (1) little bug in ParseFunction fixed
// (2) line numbers were not shown for project initialization
// 2004-10-22 2.1b support for BCB try..whatever blocks added
// 2004-07-11 2.1a (1) line numbers are added to disassembling (Delphi only)
// (2) some disassembling cleartext tweaking
// 2004-04-25 2.1 (1) structured exception handling is detected + parsed now
// (2) special support for Delphi try..except blocks
// (3) special support for Delphi try..finally blocks
// (4) special support for Delphi safecall handling blocks
// (5) Delphi @Halt call is interpreted as "end of function"
// 2004-01-01 2.0b (1) ParseFunction "not interceptable" false alarm fixed
// (2) TryRead improved
// 2003-11-10 2.0a (1) jumps/calls to the very next instruction are ignored now
// (2) text output of function parts speeded up (for madExcept)
// 2003-06-09 2.0 (1) rewritten from scratch, full support for mmx/sse2/3dnow!
// (2) now we have a full disassembler including text output
// (3) the disassembler keeps track of the register contents
// -> should improve the detection of call/jmp targets
// (4) TryRead gets rid of unwanted debugger exception warnings
// 2002-11-26 1.2c ParseFunction stops at the end of module's code section
// 2002-11-07 1.2b (1) GetImageNtHeaders + PImageExportDirectory -> madTools
// (2) ParseFunction: case/switch statements are interpreted
// (3) ParseFunction: little gaps between code areas are parsed
// 2001-07-22 1.2a all remote stuff was moved to the new package "madRemote"
// 2001-07-08 1.2 (1) CreateRemoteThread added (works also in win9x)
// (2) Alloc/FreeMemEx added
// 2001-06-04 1.1e (1) some changes in "TFunctionInfo"
// (2) ParseFunction parameter "acceptOutsideCode" added
// (3) "TCodeInfo.Call" added
// 2001-05-25 1.1d (1) only targets with 4 byte length are accepted as far calls
// (2) CopyFunction works better now inside of the IDE in win9x
// 2001-04-16 1.1c bug (relocating absolute targets) in CopyFunction fixed
// 2001-02-23 1.1b little bug in ParseFunction fixed
// 2001-01-07 1.1a FreeCopiedFunction added
// 2000-12-22 1.1 CopyFunction added and some minor changes
// 2000-11-23 1.0e minor bug fixes in ParseCode + ParseFunction
unit madDisAsm;
{$I mad.inc}
interface
uses Windows, madTypes, madTools, madStrings;
// ***************************************************************
{ $define cstyle}
{ $define amd64}
type
// result type for ParseCode
TCodeInfo = record
IsValid : boolean; // was the specified code pointer valid?
Opcode : word; // Opcode, one byte ($00xx) or two byte ($0fxx)
ModRm : byte; // ModRm byte, if available, otherwise 0
Call : boolean; // is this instruction a call?
Jmp : boolean; // is this instruction a jmp?
RelTarget : boolean; // is this target relative (or absolute)?
Target : pointer; // absolute target address
PTarget : pointer; // pointer to the target information in the code
PPTarget : TPPointer; // pointer to pointer to the target information
TargetSize : integer; // size of the target information in bytes (1/2/4)
Enlargeable : boolean; // can the target size of this opcode be extended?
This : pointer; // where does this instruction begin?
Next : pointer; // next code location
end;
// disassembles the specified "code"
// you can loop through code blocks by using "result.Next"
function ParseCode (code: pointer ) : TCodeInfo; overload;
function ParseCode (code: pointer; var disAsm: string) : TCodeInfo; overload;
type
// result type for ParseFunction
TFunctionInfo = record
IsValid : boolean;
EntryPoint : pointer;
CodeBegin : pointer;
CodeLen : integer;
LastErrorAddr : pointer;
LastErrorNo : cardinal;
LastErrorStr : string;
CodeAreas : array of record
AreaBegin : pointer;
AreaEnd : pointer;
CaseBlock : boolean;
OnExceptBlock : boolean;
CalledFrom : pointer;
Registers : array [0..{$ifdef amd64}15{$else}7{$endif}] of pointer;
end;
FarCalls : array of record
Call : boolean; // is it a CALL or a JMP?
CodeAddr1 : pointer; // beginning of call instruction
CodeAddr2 : pointer; // beginning of next instruction
Target : pointer;
RelTarget : boolean;
PTarget : pointer;
PPTarget : TPPointer;
end;
UnknownTargets : array of record
Call : boolean;
CodeAddr1 : pointer;
CodeAddr2 : pointer;
end;
Interceptable : boolean;
Copy : record
IsValid : boolean;
BufferLen : integer;
LastErrorAddr : pointer;
LastErrorNo : cardinal;
LastErrorStr : string;
end;
end;
TPFunctionInfo = ^TFunctionInfo;
// disassembles the complete function beginning at "func"
// the result tells you whether you can copy this function to another process
// (and which call targets you have to correct for this purpose)
// and whether you can intercept this function by overwriting the code
function ParseFunction (func: pointer ) : TFunctionInfo; overload;
function ParseFunction (func: pointer; var disAsm: string) : TFunctionInfo; overload;
// ***************************************************************
const
// error codes
CErrorBase_DisAsm = $770000;
CErrorNo_UnknownTarget = CErrorBase_DisAsm + 0;
CErrorNo_InvalidCode = CErrorBase_DisAsm + 1;
CErrorNo_CodeNotInterceptable = CErrorBase_DisAsm + 2;
CErrorNo_BadFunction = CErrorBase_DisAsm + 3;
CErrorNo_DoubleHook = CErrorBase_DisAsm + 4;
CErrorStr_UnknownTarget = 'This target can''t be seen in the assembler code.';
CErrorStr_InvalidCode = 'Invalid code!';
CErrorStr_CodeNotInterceptable = 'This code is not interceptable due to it''s design.';
CErrorStr_BadFunction = 'The specified function is bad.';
CErrorStr_DoubleHook = 'This code was already hooked by another hooking library.';
// ***************************************************************
// internal stuff
function kernel32handle : dword;
function ntdllhandle : dword;
function KernelProc (api: string; doubleCheck: boolean = false) : pointer;
function NtProc (api: string; doubleCheck: boolean = false) : pointer;
function GetExportDirectory (code: pointer; out module: cardinal; out pexp: PImageExportDirectory) : boolean;
function SolveW9xDebugMode (code: pointer) : pointer;
function Magic : cardinal;
function Magic95 : boolean;
function ParseCode_ (code: pointer; tryRead_: dword) : TCodeInfo;
function ParseFunction_ (func : pointer;
tryRead_ : dword;
HandleAnyExceptionAddr : pointer;
HandleOnExceptionAddr : pointer;
HandleAutoExceptionAddr : pointer;
HandleFinallyAddr : pointer;
Halt0Addr : pointer) : TFunctionInfo;
function ParseFunctionEx (func: pointer; var disAsm: string; exceptAddr: pointer;
maxLines: integer; autoDelimiters: boolean) : TFunctionInfo;
var GetProcNameFromMapFile : function (proc: pointer) : string = nil;
GetLineNumber : procedure (proc: pointer; var line: integer; var minAddr, maxAddr: pointer) = nil;
BcbInitExceptBlockLDTC : pointer = nil;
const
CKernel32 = (* kernel32.dll *) #$3E#$30#$27#$3B#$30#$39#$66#$67#$7B#$31#$39#$39;
CReadProcessMemory = (* ReadProcessMemory *) #$07#$30#$34#$31#$05#$27#$3A#$36#$30#$26#$26#$18#$30#$38#$3A#$27#$2C;
CWriteProcessMemory = (* WriteProcessMemory *) #$02#$27#$3C#$21#$30#$05#$27#$3A#$36#$30#$26#$26#$18#$30#$38#$3A#$27#$2C;
function StartTryRead : dword;
procedure EndTryRead (tryRead: dword);
function TryRead (src, dst: pointer; count: integer; tryRead: dword = 0) : boolean;
function TryWrite (src, dst: pointer; count: integer; tryRead: dword = 0) : boolean;
// ***************************************************************
implementation
{$ifdef cstyle}
function IntToHexEx(value : int64;
minLen : integer = 1;
fillChar : char = '0') : string;
begin
result := madStrings.IntToHexEx(value);
Delete(result, 1, 1);
if (minLen < 0) or (fillChar in ['0'..'9','A'..'F','a'..'f']) then begin
result := FillStr(result, minLen, fillChar);
result := UpStr(result) + 'h';
end else begin
result := UpStr(result) + 'h';
result := FillStr(result, minLen, fillChar);
end;
end;
{$endif}
// ***************************************************************
function GetHandleAnyExceptionAddr : pointer;
asm
mov eax, offset System.@HandleAnyException
end;
function GetHandleOnExceptionAddr : pointer;
asm
mov eax, offset System.@HandleOnException
end;
function GetHandleAutoExceptionAddr : pointer;
asm
mov eax, offset System.@HandleAutoException
end;
function GetHandleFinallyAddr : pointer;
asm
mov eax, offset System.@HandleFinally
end;
function GetHalt0Addr : pointer;
asm
mov eax, offset System.@Halt0
end;
// ***************************************************************
const
fInvalid = $ffff; // invalid opcode
fReg = $0007; // bit mask
fNoReg = $0000; // no register information available for this opcode
fRegAl = $0001; // no modrm byte: al register
fRegEax = $0002; // no modrm byte: (e)ax register
fRegO8 = $0004; // no modrm byte: byte register depending on opcode
fRegO32 = $0005; // no modrm byte: (d)word register depending on opcode
fRegEaxO = $0006; // no modrm byte: fRegEax + fRegO32
fRegDxA = $0007; // no modrm byte: dx register + (e)ax/al register
fReg8 = $0001; // byte register specified by modrm byte
fReg16 = $0002; // word register specified by modrm byte
fRegxx = $0003; // segment/cr/dr register specified by modrm byte
fReg32 = $0004; // (d)word register specified by modrm byte
fReg64 = $0005; // qword register specified by modrm byte
fRegSt = $0006; // st floating point register specified by modrm byte
fReg128 = $0007; // oword register specified by modrm byte
fMod = $0038; // bit mask
fModOpc = $0008; // real flags are stored in COpcodeFlagsEx
fMod8 = $0010; // byte register/memory
fMod16 = $0018; // word register/memory
fMod32 = $0020; // (d)word register/memory
fMod64 = $0028; // qword register/memory
fMod80 = $0030; // st floating point register/memory
fMod128 = $0038; // oword register/memory
f66 = $00C0; // bit mask
f66R = $0040; // 66 prefix changes size of register -> 16 (sse: 128)
f66M = $0080; // 66 prefix changes size of modrm -> 16 (sse: 128)
f66RM = $00C0; // 66 prefix changes size of reg+modrm -> 16 (sse: 128)
fPtr = $0100; // disassembler shows "xword/byte ptr" or "[$xxx]"
fOrder = $0200; // swapped order -> modrm or immediate data comes first
fI = $0C00; // bit mask
fI8 = $0400; // immediate byte available
fI16 = $0800; // immediate word available
fI32 = $0C00; // immediate (d)word available
fJmpRel = $1000; // this opcode is a relative jump/call
fClr = $e000; // bit mask
fClrR = $2000; // clear modrm register/memory specified
fClrM = $4000; // clear register specified by modrm byte
fClrO = $6000; // clear register depending on opcode
fClrA = $8000; // clear eax
fClrRM = $a000; // fClrR + fClrM
fClrMA = $c000; // fClrM + fClrA
fClrOA = $e000; // fClrO + fClrA
// flags for one byte opcodes
COpcodeFlags : array [$00..$ff] of word =
((fReg8 + fMod8 + fOrder + fClrM ), // 00 /r add r/mb, rb (r)
(fReg32 + fMod32 + f66RM + fOrder + fClrM ), // 01 /r add r/m?, r? (r)
(fReg8 + fMod8 + fClrR ), // 02 /r add rb, r/mb r
(fReg32 + fMod32 + f66RM + fClrR ), // 03 /r add r?, r/m? r
(fRegAl + fI8 + fClrA ), // 04 ib add al, ib eax
(fRegEax + f66R + fI32 + fClrA ), // 05 i? add (e)ax, i? eax
{$ifdef amd64}
(fInvalid ), // -----
(fInvalid ), // -----
{$else}
(fNoReg ), // 06 push es
(fNoReg ), // 07 pop es
{$endif}
(fReg8 + fMod8 + fOrder + fClrM ), // 08 /r or r/mb, rb (r)
(fReg32 + fMod32 + f66RM + fOrder + fClrM ), // 09 /r or r/m?, r? (r)
(fReg8 + fMod8 + fClrR ), // 0a /r or rb, r/mb r
(fReg32 + fMod32 + f66RM + fClrR ), // 0b /r or r?, r/m? r
(fRegAl + fI8 + fClrA ), // 0c ib or al, ib eax
(fRegEax + f66R + fI32 + fClrA ), // 0d i? or (e)ax, i? eax
{$ifdef amd64}
(fInvalid ), // -----
{$else}
(fNoReg ), // 0e push cs
{$endif}
(fNoReg ), // 0f < extra table below >
(fReg8 + fMod8 + fOrder + fClrM ), // 10 /r adc r/mb, rb (r)
(fReg32 + fMod32 + f66RM + fOrder + fClrM ), // 11 /r adc r/m?, r? (r)
(fReg8 + fMod8 + fClrR ), // 12 /r adc rb, r/mb r
(fReg32 + fMod32 + f66RM + fClrR ), // 13 /r adc r?, r/m? r
(fRegAl + fI8 + fClrA ), // 14 ib adc al, ib eax
(fRegEax + f66R + fI32 + fClrA ), // 15 i? adc (e)ax, i? eax
{$ifdef amd64}
(fInvalid ), // -----
(fInvalid ), // -----
{$else}
(fNoReg ), // 16 push ss
(fNoReg ), // 17 pop ss
{$endif}
(fReg8 + fMod8 + fOrder + fClrM ), // 18 /r sbb r/mb, rb (r)
(fReg32 + fMod32 + f66RM + fOrder + fClrM ), // 19 /r sbb r/m?, i? (r)
(fReg8 + fMod8 + fClrR ), // 1a /r sbb rb, r/mb r
(fReg32 + fMod32 + f66RM + fClrR ), // 1b /r sbb r?, r/m? r
(fRegAl + fI8 + fClrA ), // 1c ib sbb al, ib eax
(fRegEax + f66R + fI32 + fClrA ), // 1d i? sbb (e)ax, i? eax
{$ifdef amd64}
(fInvalid ), // -----
(fInvalid ), // -----
{$else}
(fNoReg ), // 1e push ds
(fNoReg ), // 1f pop ds
{$endif}
(fReg8 + fMod8 + fOrder + fClrM ), // 20 /r and r/mb, rb (r)
(fReg32 + fMod32 + f66RM + fOrder + fClrM ), // 21 /r and r/m?, r? (r)
(fReg8 + fMod8 + fClrR ), // 22 /r and rb, r/mb r
(fReg32 + fMod32 + f66RM + fClrR ), // 23 /r and r?, r/m? r
(fRegAl + fI8 + fClrA ), // 24 ib and al, ib eax
(fRegEax + f66R + fI32 + fClrA ), // 25 i? and (e)ax, i? eax
(fNoReg ), // 26 PREFIX: es segment override
{$ifdef amd64}
(fInvalid ), // -----
{$else}
(fNoReg + fClrA ), // 27 daa eax
{$endif}
(fReg8 + fMod8 + fOrder + fClrM ), // 28 /r sub r/mb, rb (r)
(fReg32 + fMod32 + f66RM + fOrder + fClrM ), // 29 /r sub r/m?, r? (r)
(fReg8 + fMod8 + fClrR ), // 2a /r sub rb, r/mb r
(fReg32 + fMod32 + f66RM + fClrR ), // 2b /r sub r?, r/m? r
(fRegAl + fI8 + fClrA ), // 2c ib sub al, ib eax
(fRegEax + f66R + fI32 + fClrA ), // 2d i? sub (e)ax, i? eax
(fNoReg ), // 2e PREFIX: cs segment override / branch not taken hint
{$ifdef amd64}
(fInvalid ), // -----
{$else}
(fNoReg + fClrA ), // 2f das eax
{$endif}
(fReg8 + fMod8 + fOrder + fClrM ), // 30 /r xor r/mb, rb (r)
(fReg32 + fMod32 + f66RM + fOrder + fClrM ), // 31 /r xor r/m?, r? (r)
(fReg8 + fMod8 + fClrR ), // 32 /r xor rb, r/mb r
(fReg32 + fMod32 + f66RM + fClrR ), // 33 /r xor r?, r/m? r
(fRegAl + fI8 + fClrA ), // 34 ib xor al, ib eax
(fRegEax + f66R + fI32 + fClrA ), // 35 i? xor (e)ax, i? eax
(fNoReg ), // 36 PREFIX: SS segment override
{$ifdef amd64}
(fInvalid ), // -----
{$else}
(fNoReg + fClrA ), // 37 aaa eax
{$endif}
(fReg8 + fMod8 + fOrder ), // 38 /r cmp r/mb, rb
(fReg32 + fMod32 + f66RM + fOrder ), // 39 /r cmp r/m?, r?
(fReg8 + fMod8 ), // 3a /r cmp rb, r/mb
(fReg32 + fMod32 + f66RM ), // 3b /r cmp r?, r/m?
(fRegAl + fI8 ), // 3c ib cmp al, ib
(fRegEax + f66R + fI32 ), // 3d i? cmp (e)ax, i?
(fNoReg ), // 3e PREFIX: DS segment override / branch taken hint
{$ifdef amd64}
(fInvalid ), // -----
{$else}
(fNoReg + fClrA ), // 3f aas eax
{$endif}
{$ifdef amd64}
(fNoReg ), // 40 PREFIX: REX
(fNoReg ), // 41
(fNoReg ), // 42
(fNoReg ), // 43
(fNoReg ), // 44
(fNoReg ), // 45
(fNoReg ), // 46
(fNoReg ), // 47
(fNoReg ), // 48
(fNoReg ), // 49
(fNoReg ), // 4a
(fNoReg ), // 4b
(fNoReg ), // 4c
(fNoReg ), // 4d
(fNoReg ), // 4e
(fNoReg ), // 4f
{$else}
(fRegO32 + f66R + fClrO ), // 40 inc (e)ax r
(fRegO32 + f66R + fClrO ), // 41 inc (e)cx r
(fRegO32 + f66R + fClrO ), // 42 inc (e)dx r
(fRegO32 + f66R + fClrO ), // 43 inc (e)bx r
(fRegO32 + f66R + fClrO ), // 44 inc (e)sp r
(fRegO32 + f66R + fClrO ), // 45 inc (e)bp r
(fRegO32 + f66R + fClrO ), // 46 inc (e)si r
(fRegO32 + f66R + fClrO ), // 47 inc (e)di r
(fRegO32 + f66R + fClrO ), // 48 dec (e)ax r
(fRegO32 + f66R + fClrO ), // 49 dec (e)cx r
(fRegO32 + f66R + fClrO ), // 4a dec (e)dx r
(fRegO32 + f66R + fClrO ), // 4b dec (e)bx r
(fRegO32 + f66R + fClrO ), // 4c dec (e)sp r
(fRegO32 + f66R + fClrO ), // 4d dec (e)bp r
(fRegO32 + f66R + fClrO ), // 4e dec (e)si r
(fRegO32 + f66R + fClrO ), // 4f dec (e)di r
{$endif}
(fRegO32 + f66R ), // 50 push (e)ax
(fRegO32 + f66R ), // 51 push (e)cx
(fRegO32 + f66R ), // 52 push (e)dx
(fRegO32 + f66R ), // 53 push (e)bx
(fRegO32 + f66R ), // 54 push (e)sp
(fRegO32 + f66R ), // 55 push (e)bp
(fRegO32 + f66R ), // 56 push (e)si
(fRegO32 + f66R ), // 57 push (e)di
(fRegO32 + f66R + fClrO ), // 58 pop (e)ax r
(fRegO32 + f66R + fClrO ), // 59 pop (e)cx r
(fRegO32 + f66R + fClrO ), // 5a pop (e)dx r
(fRegO32 + f66R + fClrO ), // 5b pop (e)bx r
(fRegO32 + f66R + fClrO ), // 5c pop (e)sp r
(fRegO32 + f66R + fClrO ), // 5d pop (e)bp r
(fRegO32 + f66R + fClrO ), // 5e pop (e)si r
(fRegO32 + f66R + fClrO ), // 5f pop (e)di r
{$ifdef amd64}
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fReg32 + fMod32 + f66R + fPtr + fClrR ), // 63 /r movsxd rq, r/md r
{$else}
(fNoReg ), // 60 pusha(d)
(fNoReg + fClrA ), // 61 popa(d) edi esi ebp ebx edx ecx eax
(fReg32 + fMod32 + f66RM ), // 62 /r bound r?, m?&?
(fReg16 + fMod16 + fOrder + fClrM ), // 63 /r arpl r/mw, rw (r)
{$endif}
(fNoReg ), // 64 PREFIX: fs segment override
(fNoReg ), // 65 PREFIX: gs segment override
(fNoReg ), // 66 PREFIX: operand size override
(fNoReg ), // 67 PREFIX: address size override
(fNoReg + fI32 ), // 68 i? push i?
(fReg32 + fMod32 + f66RM + fI32 + fClrR ), // 69 /r i? imul r?, [r/m?,] i? r
(fNoReg + fI8 ), // 6a ib push ib
(fReg32 + fMod32 + f66RM + fI8 + fClrR ), // 6b /r ib imul r?, [r/m?,] ib r
(fNoReg ), // 6c insb edi
(fNoReg ), // 6d insw/insd edi
(fNoReg ), // 6e outsb esi
(fNoReg ), // 6f outsw/d esi
(fNoReg + fI8 + fJmpRel ), // 70 cb jo relb
(fNoReg + fI8 + fJmpRel ), // 71 cb jno relb
(fNoReg + fI8 + fJmpRel ), // 72 cb jb relb
(fNoReg + fI8 + fJmpRel ), // 73 cb jnb relb
(fNoReg + fI8 + fJmpRel ), // 74 cb jz relb
(fNoReg + fI8 + fJmpRel ), // 75 cb jnz relb
(fNoReg + fI8 + fJmpRel ), // 76 cb jbe relb
(fNoReg + fI8 + fJmpRel ), // 77 cb ja relb
(fNoReg + fI8 + fJmpRel ), // 78 cb js relb
(fNoReg + fI8 + fJmpRel ), // 79 cb jns relb
(fNoReg + fI8 + fJmpRel ), // 7a cb jp relb
(fNoReg + fI8 + fJmpRel ), // 7b cb jnp relb
(fNoReg + fI8 + fJmpRel ), // 7c cb jl relb
(fNoReg + fI8 + fJmpRel ), // 7d cb jge relb
(fNoReg + fI8 + fJmpRel ), // 7e cb jle relb
(fNoReg + fI8 + fJmpRel ), // 7f cb jg relb
(fNoReg + fMod8 + fPtr + fI8 ), // 80 /x ib xxx r/mb, ib (r) - add/or/adc/sbb/and/sub/xor/cmp
(fNoReg + fMod32 + f66M + fPtr + fI32 ), // 81 /x i? xxx r/m?, i? (r)
{$ifdef amd64}
(fInvalid ), // -----
{$else}
(fNoReg + fMod8 + fPtr + fI8 ), // 82 /x ib xxx r/mb, ib (r)
{$endif}
(fNoReg + fMod32 + f66M + fPtr + fI8 ), // 83 /x ib xxx r/m?, ib (r)
(fReg8 + fMod8 + fOrder ), // 84 /r test r/mb, rb
(fReg32 + fMod32 + f66RM + fOrder ), // 85 /r test r/m?, r?
(fReg8 + fMod8 + fClrRM), // 86 /r xchg rb, r/mb (r) r
(fReg32 + fMod32 + f66RM + fClrRM), // 87 /r xchg r?, r/m? (r) r
(fReg8 + fMod8 + fOrder + fClrM ), // 88 /r mov r/mb, rb (r)
(fReg32 + fMod32 + f66RM + fOrder + fClrM ), // 89 /r mov r/m?, r? (r)
(fReg8 + fMod8 + fClrR ), // 8a /r mov rb, r/mb r
(fReg32 + fMod32 + f66RM + fClrR ), // 8b /r mov r?, r/m? r
(fRegxx + fMod32 + f66RM + fOrder + fClrM ), // 8c /r mov r/m?, sreg (r)
(fReg32 + fMod32 + f66RM + fClrR ), // 8d /r lea r?, m r
(fRegxx + fMod16 + f66RM + fPtr ), // 8e /r mov sreg, r/m?
(fNoReg + fMod32 + f66M + fPtr ), // 8f /0 pop m?
(fNoReg ), // 90 nop
(fRegEaxO+ f66R + fClrOA), // 91 xchg (e)ax, (e)cx r eax
(fRegEaxO+ f66R + fClrOA), // 92 xchg (e)ax, (e)dx r eax
(fRegEaxO+ f66R + fClrOA), // 93 xchg (e)ax, (e)bx r eax
(fRegEaxO+ f66R + fClrOA), // 94 xchg (e)ax, (e)sp r eax
(fRegEaxO+ f66R + fClrOA), // 95 xchg (e)ax, (e)bp r eax
(fRegEaxO+ f66R + fClrOA), // 96 xchg (e)ax, (e)si r eax
(fRegEaxO+ f66R + fClrOA), // 97 xchg (e)ax, (e)di r eax
(fNoReg + fClrA ), // 98 cbw/cwde eax
(fNoReg ), // 99 cwd/cdq edx
{$ifdef amd64}
(fInvalid ), // -----
{$else}
(fNoReg ), // 9a c? cw call cw:c?
{$endif}
(fNoReg ), // 9b wait
(fNoReg ), // 9c pushf(d)
(fNoReg ), // 9d popf(d)
(fNoReg ), // 9e sahf
(fNoReg + fClrA ), // 9f lahf eax
(fRegAl + fPtr + fClrA ), // a0 mov al, moffsb eax
(fRegEax + f66R + fPtr + fClrA ), // a1 mov (e)ax, moffs? eax
(fRegAl + fPtr + fOrder ), // a2 mov moffsb, al
(fRegEax + f66R + fPtr + fOrder ), // a3 mov moffs?, (e)ax
(fNoReg ), // a4 movsb esi edi
(fNoReg ), // a5 movsw/d esi edi
(fNoReg ), // a6 cmpsb esi edi
(fNoReg ), // a7 cmpsd/w esi edi
(fRegAl + fI8 ), // a8 ib test al, ib
(fRegEax + f66R + fI32 ), // a9 i? test (e)ax, i?
(fNoReg ), // aa stosb edi
(fNoReg ), // ab stosw/d edi
(fNoReg + fClrA ), // ac lodsb eax esi
(fNoReg + fClrA ), // ad lodsw/d eax esi
(fNoReg ), // ae scasb edi
(fNoReg ), // af scasw/d edi
(fRegO8 + fI8 + fClrO ), // b0 ib mov rb, ib r
(fRegO8 + fI8 + fClrO ), // b1 ib mov rb, ib r
(fRegO8 + fI8 + fClrO ), // b2 ib mov rb, ib r
(fRegO8 + fI8 + fClrO ), // b3 ib mov rb, ib r
(fRegO8 + fI8 + fClrO ), // b4 ib mov rb, ib r
(fRegO8 + fI8 + fClrO ), // b5 ib mov rb, ib r
(fRegO8 + fI8 + fClrO ), // b6 ib mov rb, ib r
(fRegO8 + fI8 + fClrO ), // b7 ib mov rb, ib r
(fRegO32 + f66R + fI32 + fClrO ), // b8 i? mov (e)ax, i? r
(fRegO32 + f66R + fI32 + fClrO ), // b9 i? mov (e)cx, i? r
(fRegO32 + f66R + fI32 + fClrO ), // ba i? mov (e)dx, i? r
(fRegO32 + f66R + fI32 + fClrO ), // bb i? mov (e)bx, i? r
(fRegO32 + f66R + fI32 + fClrO ), // bc i? mov (e)sp, i? r
(fRegO32 + f66R + fI32 + fClrO ), // bd i? mov (e)bp, i? r
(fRegO32 + f66R + fI32 + fClrO ), // be i? mov (e)si, i? r
(fRegO32 + f66R + fI32 + fClrO ), // bf i? mov (e)di, i? r
(fNoReg + fMod8 + fPtr + fI8 + fClrM ), // c0 /x ib xxx r/mb, ib (r) - rol/ror/rcl/rcr/shl/shr/sar
(fNoReg + fMod32 + f66M + fPtr + fI8 + fClrM ), // c1 /x ib xxx r/m?, ib (r)
(fNoReg + fI16 ), // c2 iw ret iw
(fNoReg ), // c3 ret
{$ifdef amd64}
(fInvalid ), // -----
(fInvalid ), // -----
{$else}
(fReg32 + fMod32 + f66RM + fClrR ), // c4 /r les r?, m16:? r
(fReg32 + fMod32 + f66RM + fClrR ), // c5 /r lds r?, m16:? r
{$endif}
(fNoReg + fMod8 + fPtr + fI8 + fClrM ), // c6 /0 ib mov r/mb, ib (r)
(fNoReg + fMod32 + f66M + fPtr + fI32 + fClrM ), // c7 /0 i? mov r/m?, i? (r)
(fNoReg ), // c8 iw ib enter iw, ib ebp
(fNoReg ), // c9 leave ebp
(fNoReg + fI16 ), // ca iw ret iw
(fNoReg ), // cb ret
(fNoReg ), // cc int 3
(fNoReg + fI8 ), // cd ib int ib
{$ifdef amd64}
(fInvalid ), // -----
{$else}
(fNoReg ), // ce into
{$endif}
(fNoReg ), // cf iret(d)
(fNoReg + fMod8 + fPtr + fClrM ), // d0 /x xxx r/mb, 1 (r) - rol/ror/rcl/rcr/shl/shr/sar
(fNoReg + fMod32 + f66M + fPtr + fClrM ), // d1 /x xxx r/m?, 1 (r)
(fNoReg + fMod8 + fPtr + fClrM ), // d2 /x xxx r/mb, cl (r)
(fNoReg + fMod32 + f66M + fPtr + fClrM ), // d3 /x xxx r/m?, cl (r)
{$ifdef amd64}
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
{$else}
(fNoReg + fI8 + fClrA ), // d4 ib aam eax
(fNoReg + fI8 + fClrA ), // d5 ib aad eax
(fNoReg ), // d6 salc
{$endif}
(fNoReg + fClrA ), // d7 xlatb eax
(fModOpc ), // d8 /r xxx mdreal/st, st(1)
(fModOpc ), // d9 /x/r xxx
(fModOpc ), // da /x/r xxx
(fModOpc ), // db /x/r xxx
(fModOpc ), // dc /r xxx mdreal/st(1), st
(fModOpc ), // dd /x/r xxx
(fModOpc ), // de /x/r xxx
(fModOpc ), // df /x/r xxx
(fNoReg + fI8 + fJmpRel ), // e0 cb loopne relb ecx
(fNoReg + fI8 + fJmpRel ), // e1 cb loope relb ecx
(fNoReg + fI8 + fJmpRel ), // e2 cb loop relb ecx
(fNoReg + fI8 + fJmpRel ), // e3 cb jcxz relb
(fRegAl + fI8 + fClrA ), // e4 ib in al, ib eax
(fRegEax + f66R + fI8 + fClrA ), // e5 ib in (e)ax, ib eax
(fRegAl + fOrder + fI8 ), // e6 ib out ib, al
(fRegEax + f66R + fOrder + fI8 ), // e7 ib out ib, (e)ax
(fNoReg + fI32 + fJmpRel ), // e8 c? call rel?
(fNoReg + fI32 + fJmpRel ), // e9 c? jmp rel?
{$ifdef amd64}
(fInvalid ), // -----
{$else}
(fNoReg ), // ea c? cw jmp ptr16:?
{$endif}
(fNoReg + fI8 + fJmpRel ), // eb cb jmp relb
(fRegDxA + fClrA ), // ec in al, dx eax
(fRegDxA + f66R + fClrA ), // ed in (e)ax, dx eax
(fRegDxA + fOrder ), // ee out dx, al
(fRegDxA + f66R + fOrder ), // ef out dx, (e)ax
(fNoReg ), // f0 PREFIX: lock
(fNoReg ), // f1 int01
(fNoReg ), // f2 PREFIX: repne +ecx
(fNoReg ), // f3 PREFIX: rep(e) +ecx
(fNoReg ), // f4 hlt
(fNoReg ), // f5 cmc
(fModOpc ), // f6 /x (ib) xxx r/mb (,ib) (r) (eax) - test/not/neg/mul/imul/div/idiv
(fModOpc ), // f7 /x (i?) xxx r/m? (,i?) (r) (eax)
(fNoReg ), // f8 clc
(fNoReg ), // f9 stc
(fNoReg ), // fa cli
(fNoReg ), // fb sti
(fNoReg ), // fc cld
(fNoReg ), // fd std
(fNoReg + fMod8 + fPtr + fClrM ), // fe /x xxx r/mb (r) - inc/dec
(fNoReg + fMod32 + f66M + fPtr )); // ff /x xxx r/m? (r) - inc/dec/call/call/jmp/jmp/push
// flags for two byte opcodes ($0f $xx)
COpcodeFlags0f : array [$00..$ff] of word =
((fNoReg + fMod16 + fPtr ), // 0f 00 /x xxx r/mw (r) - sldt/str/lldt/ltr/verr/verw
(fNoReg + fMod16 ), // 0f 01 /x xxx r/m? (r) - sgdt/sidt/lgdt/lidt/smsw/-/lmsw/invlpg
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 02 /r lar r?, r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 03 /r lsl r?, r/m? r
(fInvalid ), // -----
(fNoReg ), // 0f 05 syscall (AMD)
(fNoReg ), // 0f 06 clts
(fNoReg ), // 0f 07 sysret (AMD)
(fNoReg ), // 0f 08 invd
(fNoReg ), // 0f 09 wbinvd
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fNoReg + fMod8 + fPtr ), // 0f 0d /x prefetch(w) r/mb
(fNoReg ), // 0f 0e femms
(fReg64 + fMod64 + fPtr + fI8 ), // 0f 0f xx xxx pq, qq
(fReg128 + fMod128 ), // 0f 10 /r movups xmm, xmm/m
(fReg128 + fMod128 + fOrder ), // 0f 11 /r movups xmm/m, xmm
(fReg128 + fMod128 ), // 0f 12 /r movlps xmm, m
(fReg128 + fMod128 + fOrder ), // 0f 13 /r movlps m, xmm
(fReg128 + fMod128 ), // 0f 14 /r unpcklps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 15 /r unpckhps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 16 /r movhps xmm, m
(fReg128 + fMod128 + fOrder ), // 0f 17 /r movhps m, xmm
(fNoReg + fMod8 + fPtr ), // 0f 18 /x prefetchxxx
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fRegxx + fMod32 + fOrder + fClrM ), // 0f 20 /r mov rd, cr0-4 r
(fRegxx + fMod32 + fOrder + fClrM ), // 0f 21 /r mov rd, dr0-7 r
(fRegxx + fMod32 ), // 0f 22 /r mov cr0-4, rd
(fRegxx + fMod32 ), // 0f 23 /r mov dr0-7, rd
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fReg128 + fMod128 ), // 0f 28 /r movaps xmm, xmm/m
(fReg128 + fMod128 + fOrder ), // 0f 29 /r movaps xmm/m, xmm
(fReg128 + fMod64 ), // 0f 2a /r cvtpi2ps xmm, mm/r/m
(fReg128 + fMod128 + fOrder ), // 0f 2b /r movntps m, xmm
(fReg64 + fMod128 ), // 0f 2c /r cvttps2pi m/r, xmm/m (r)
(fReg64 + fMod128 ), // 0f 2d /r cvtps2pi m/r, xmm/m (r)
(fReg128 + fMod128 ), // 0f 2e /r ucomiss xmm, xmm/m
(fReg128 + fMod128 ), // 0f 2f /r comiss xmm, xmm/m
(fNoReg ), // 0f 30 wrmsr
(fNoReg + fClrA ), // 0f 31 rdtsc edx eax
(fNoReg + fClrA ), // 0f 32 rdmsr edx eax
(fNoReg + fClrA ), // 0f 33 rdpmc edx eax
(fNoReg ), // 0f 34 sysenter
(fNoReg ), // 0f 35 sysexit
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 40 /r cmovo r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 41 /r cmovno r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 42 /r cmovb r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 43 /r cmovnb r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 44 /r cmovz r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 45 /r cmovnz r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 46 /r cmovbe r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 47 /r cmova r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 48 /r cmovs r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 49 /r cmovns r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 4a /r cmovp r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 4b /r cmovnp r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 4c /r cmovl r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 4d /r cmovge r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 4e /r cmovle r?,r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f 4f /r cmovg r?,r/m? r
(fReg32 + fMod128 + fClrM ), // 0f 50 /r movmskps r, xmm r
(fReg128 + fMod128 ), // 0f 51 /r sqrtps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 52 /r rsqrtps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 53 /r rcpps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 54 /r andps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 55 /r andnps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 56 /r orps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 57 /r xorps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 58 /r addps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 59 /r mulps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 5a /r cvtps2pd xmm, xmm/m
(fReg128 + fMod128 ), // 0f 5b /r cvtdq2ps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 5c /r subps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 5d /r minps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 5e /r divps xmm, xmm/m
(fReg128 + fMod128 ), // 0f 5f /r maxps xmm, xmm/m
(fReg64 + fMod64 + f66RM ), // 0f 60 /r punpcklbw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f 61 /r punpcklwd mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f 62 /r punpckldq mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f 63 /r packsswb mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f 64 /r pcmpgtb mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f 65 /r pcmpgtw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f 66 /r pcmpgtd mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f 67 /r packuswb mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f 68 /r punpckhbw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f 69 /r punpckhwd mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f 6a /r punpckhdq mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f 6b /r packssdw mm1, mm/m
(fReg64 + fMod64 + f66RM ), // 0f 6c /r punpcklqdq xmm, xmm/m
(fReg64 + fMod64 + f66RM ), // 0f 6d /r punpckhqdq xmm, xmm/m
(fReg64 + fMod32 + f66R ), // 0f 6e /r movd mm, r/md
(fReg64 + fMod64 + f66RM ), // 0f 6f /r movq mm, mm/m
(fReg64 + fMod64 + f66RM + fI8 ), // 0f 70 /r ib pshufw mm, mm/m, ib
(fNoReg + fMod64 + f66M + fI8 ), // 0f 71 /x ib xxx (x)mm, ib
(fNoReg + fMod64 + f66M + fI8 ), // 0f 72 /x ib xxx (x)mm, ib
(fNoReg + fMod64 + f66M + fI8 ), // 0f 73 /x ib xxx (x)mm, ib
(fReg64 + fMod64 + f66RM ), // 0f 74 /r pcmpeqb mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f 75 /r pcmpeqw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f 76 /r pcmpeqd mm, mm/m
(fNoReg ), // 0f 77 emms
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fInvalid ), // -----
(fReg128 + fMod128 + f66RM ), // 0f 7c /r haddpd xmm, xmm/m
(fReg128 + fMod128 + f66RM ), // 0f 7d /r hsubpd xmm, xmm/m
(fReg64 + fMod32 + f66R + fOrder ), // 0f 7e /r movd r/md, mm (r)
(fReg64 + fMod64 + f66RM + fOrder ), // 0f 7f /r movq mm/m, mm
(FNoReg + fI32 + fJmpRel ), // 0f 80 c? jo relb
(FNoReg + fI32 + fJmpRel ), // 0f 81 c? jno relb
(FNoReg + fI32 + fJmpRel ), // 0f 82 c? jb relb
(FNoReg + fI32 + fJmpRel ), // 0f 83 c? jnb relb
(FNoReg + fI32 + fJmpRel ), // 0f 84 c? jz relb
(FNoReg + fI32 + fJmpRel ), // 0f 85 c? jnz relb
(FNoReg + fI32 + fJmpRel ), // 0f 86 c? jbe relb
(FNoReg + fI32 + fJmpRel ), // 0f 87 c? ja relb
(FNoReg + fI32 + fJmpRel ), // 0f 88 c? js relb
(FNoReg + fI32 + fJmpRel ), // 0f 89 c? jns relb
(FNoReg + fI32 + fJmpRel ), // 0f 8a c? jp relb
(FNoReg + fI32 + fJmpRel ), // 0f 8b c? jnp relb
(FNoReg + fI32 + fJmpRel ), // 0f 8c c? jl relb
(FNoReg + fI32 + fJmpRel ), // 0f 8d c? jge relb
(FNoReg + fI32 + fJmpRel ), // 0f 8e c? jle relb
(FNoReg + fI32 + fJmpRel ), // 0f 8f c? jg relb
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 90 seto r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 91 setno r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 92 setb r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 93 setae r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 94 sete r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 95 setne r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 96 setbe r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 97 seta r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 98 sets r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 99 setns r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 9a setp r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 9b setnp r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 9c setl r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 9d setge r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 9e setle r/mb (r)
(fNoReg + fMod8 + fPtr + fClrM ), // 0f 9f setg r/mb (r)
(fNoReg ), // 0f a0 push fs
(fNoReg ), // 0f a1 pop fs
(fNoReg + fClrA ), // 0f a2 cpuid eax ebx ecx edx
(fReg32 + fMod32 + f66RM + fOrder ), // 0f a3 bt r/m?, r?
(fReg32 + fMod32 + f66RM + fPtr + fOrder + fI8 + fClrM ), // 0f a4 ib shld r/m?, r?, ib (r)
(fReg32 + fMod32 + f66RM + fPtr + fOrder + fClrM ), // 0f a5 shld r/m?, r?, cl (r)
(fReg8 + fMod8 + fOrder + fClrMA), // 0f a6 /r cmpxchg r/mb, rb (r) eax
(fReg32 + fMod32 + f66RM + fOrder + fClrMA), // 0f a7 /r cmpxchg r/m?, r? (r) eax
(fNoReg ), // 0f a8 push gs
(fNoReg ), // 0f a9 pop gs
(fNoReg ), // 0f aa rsm
(fReg32 + fMod32 + f66RM + fOrder + fClrM ), // 0f ab bts r/m?, r? (r)
(fReg32 + fMod32 + f66RM + fPtr + fOrder + fI8 + fClrM ), // 0f ac ib shrd r/m?, r?, ib (r)
(fReg32 + fMod32 + f66RM + fPtr + fOrder + fClrM ), // 0f ad shrd r/m?, r?, cl (r)
(fNoReg + fMod32 ), // 0f ae /x xxx (m)
(fReg32 + fMod32 + f66RM + fClrR ), // 0f af /r imul r?, r/m? r
(fReg8 + fMod8 + fOrder + fClrMA), // 0f b0 /r cmpxchg r/mb, rb (r) eax
(fReg32 + fMod32 + f66RM + fOrder + fClrMA), // 0f b1 /r cmpxchg r/m?, r? (r) eax
(fReg32 + fMod32 + f66RM + fClrR ), // 0f b2 /r lss r?, m16:? r
(fReg32 + fMod32 + f66RM + fOrder + fClrM ), // 0f b3 btr r/m?, r? (r)
(fReg32 + fMod32 + f66RM + fClrR ), // 0f b4 /r lfs r?, m16:? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f b5 /r lgs r?, m16:? r
(fReg32 + fMod8 + f66R + fPtr + fClrR ), // 0f b6 /r movzx r?, r/mb r
(fReg32 + fMod16 + f66R + fPtr + fClrR ), // 0f b7 /r movzx rd, r/mw r
(fInvalid ), // -----
(fInvalid ), // -----
(fNoReg + fMod32 + f66M + fPtr + fI8 ), // 0f ba /x ib btx r/m?, ib (r) - bt/bts/btr/btc
(fReg32 + fMod32 + f66RM + fOrder + fClrM ), // 0f bb btc r/m?, r? (r)
(fReg32 + fMod32 + f66RM + fClrR ), // 0f bc bsf r?, r/m? r
(fReg32 + fMod32 + f66RM + fClrR ), // 0f bd bsr r?, r/m? r
(fReg32 + fMod8 + f66R + fPtr + fClrR ), // 0f be /r movsx r?, r/mb r
(fReg32 + fMod16 + f66R + fPtr + fClrR ), // 0f bf /r movsx rd, r/mw r
(fReg8 + fMod8 + fOrder + fClrRM), // 0f c0 /r xadd r/mb, rb (r) r
(fReg32 + fMod32 + f66RM + fOrder + fClrRM), // 0f c1 /r xadd r/m?, r? (r) r
(fReg128 + fMod128 + fI8 ), // 0f c2 /r ib cmpps xmm, xmm/m, ib
(fReg32 + fMod32 + fOrder ), // 0f c3 /r movnti md, rd
(fReg64 + fMod32 + f66R + fI8 ), // 0f c4 /r ib pinsrw mm, rd/mw, ib
(fReg32 + fMod64 + f66M + fI8 + fClrR ), // 0f c5 /r ib pextrw rd, mm, ib r
(fReg128 + fMod128 + fI8 ), // 0f c6 /r ib shufps xmm, xmm/m, ib
(fNoReg + fMod64 + fPtr + fClrA ), // 0f c7 /1 mq cmpxchg8b mq edx eax
(fRegO32 + fClrO ), // 0f c8 bswap (e)ax r
(fRegO32 + fClrO ), // 0f c9 bswap (e)cx r
(fRegO32 + fClrO ), // 0f ca bswap (e)dx r
(fRegO32 + fClrO ), // 0f cb bswap (e)bx r
(fRegO32 + fClrO ), // 0f cc bswap (e)sp r
(fRegO32 + fClrO ), // 0f cd bswap (e)bp r
(fRegO32 + fClrO ), // 0f ce bswap (e)si r
(fRegO32 + fClrO ), // 0f cf bswap (e)di r
(fReg128 + fMod128 + f66RM ), // 0f d0 /r addsubpd xmm, xmm/m
(fReg64 + fMod64 + f66RM ), // 0f d1 /r psrlw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f d2 /r psrld mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f d3 /r psrlq mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f d4 /r paddq mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f d5 /r pmullw mm, mm/m
(fReg64 + fMod64 + f66RM + fOrder ), // 0f d6 /r movq xmm/m, xmm
(fReg32 + fMod64 + f66M + fClrR ), // 0f d7 /r pmovmskb rd, mm r
(fReg64 + fMod64 + f66RM ), // 0f d8 /r psubusb mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f d9 /r psubusw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f da /r pminub mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f db /r pand mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f dc /r paddusb mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f dd /r paddusw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f de /r pmaxub mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f df /r pandn mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f e0 /r pavgb mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f e1 /r psraw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f e2 /r psrad mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f e3 /r pavgw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f e4 /r pmulhuw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f e5 /r pmulhw mm, mm/m
(fReg128 + fMod128 ), // 0f e6 /r cvttpd2dq xmm, xmm/m
(fReg64 + fMod64 + f66RM + fOrder ), // 0f e7 /r movntq m, mm
(fReg64 + fMod64 + f66RM ), // 0f e8 /r psubsb mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f e9 /r psubsw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f ea /r pminsw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f eb /r por mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f ec /r paddsb mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f ed /r paddsw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f ee /r pmaxsw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f ef /r pxor mm, mm/m
(fReg128 + fMod128 ), // 0f f0 /r lddqu xmm, m
(fReg64 + fMod64 + f66RM ), // 0f f1 /r psllw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f f2 /r pslld mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f f3 /r psllq mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f f4 /r pmuludq mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f f5 /r pmaddwd mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f f6 /r psadbw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f f7 /r maskmovq mm, mm
(fReg64 + fMod64 + f66RM ), // 0f f8 /r psubb mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f f9 /r psubw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f fa /r psubd mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f fb /r psubq mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f fc /r paddb mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f fd /r paddw mm, mm/m
(fReg64 + fMod64 + f66RM ), // 0f fe /r paddd mm, mm/m
(fNoReg )); // -----
// flags for some opcodes which differ a lot depending on the modrm byte
COpcodeFlagsEx : array [0..9] of record
opcode : byte;
flags : array [0..15] of word;
end =
((opcode : $f6;
flags : (fNoReg + fMod8 + fPtr + fI8, // f6 /0 ib test r/mb, ib
fInvalid, // -----
fNoReg + fMod8 + fPtr + fClrM, // f6 /2 not r/mb (r)
fNoReg + fMod8 + fPtr + fClrM, // f6 /3 neg r/mb (r)
fNoReg + fMod8 + fPtr + fClrA, // f6 /4 mul r/mb eax
fNoReg + fMod8 + fPtr + fClrA, // f6 /5 imul r/mb eax
fNoReg + fMod8 + fPtr + fClrA, // f6 /6 div r/mb eax
fNoReg + fMod8 + fPtr + fClrA, // f6 /7 idiv r/mb eax
fNoReg + fMod8 + fPtr + fI8,
fInvalid,
fNoReg + fMod8 + fPtr + fClrM,
fNoReg + fMod8 + fPtr + fClrM,
fNoReg + fMod8 + fPtr + fClrA,
fNoReg + fMod8 + fPtr + fClrA,
fNoReg + fMod8 + fPtr + fClrA,
fNoReg + fMod8 + fPtr + fClrA)),
(opcode : $f7;
flags : (fNoReg + fMod32 + f66M + fPtr + fI32, // f7 /0 i? test r/m?, i?
fInvalid, // -----
fNoReg + fMod32 + f66M + fPtr + fClrM, // f7 /2 not r/m? (r)
fNoReg + fMod32 + f66M + fPtr + fClrM, // f7 /3 neg r/m? (r)
fNoReg + fMod32 + f66M + fPtr + fClrA, // f7 /4 mul r/m? eax edx
fNoReg + fMod32 + f66M + fPtr + fClrA, // f7 /5 imul r/m? eax edx
fNoReg + fMod32 + f66M + fPtr + fClrA, // f7 /6 div r/m? eax edx
fNoReg + fMod32 + f66M + fPtr + fClrA, // f7 /7 idiv r/m? eax edx
fNoReg + fMod32 + f66M + fPtr + fI32,
fInvalid,
fNoReg + fMod32 + f66M + fPtr + fClrM,
fNoReg + fMod32 + f66M + fPtr + fClrM,
fNoReg + fMod32 + f66M + fPtr + fClrA,
fNoReg + fMod32 + f66M + fPtr + fClrA,
fNoReg + fMod32 + f66M + fPtr + fClrA,
fNoReg + fMod32 + f66M + fPtr + fClrA)),
(opcode : $d8;
flags : (fNoReg + fMod32 + fPtr, // d8 /0 fadd mdreal
fNoReg + fMod32 + fPtr, // d8 /1 fmul mdreal
fNoReg + fMod32 + fPtr, // d8 /2 fcom mdreal
fNoReg + fMod32 + fPtr, // d8 /3 fcomp mdreal
fNoReg + fMod32 + fPtr, // d8 /4 fsub mdreal
fNoReg + fMod32 + fPtr, // d8 /5 fsubr mdreal
fNoReg + fMod32 + fPtr, // d8 /6 fdiv mdreal
fNoReg + fMod32 + fPtr, // d8 /7 fdivr mdreal
fRegSt + fMod80, // d8 c0+i fadd st(0), st(i)
fRegSt + fMod80, // d8 c8+i fmul st(0), st(i)
fNoReg + fMod80, // d8 d0+i fcom st(i)
fNoReg + fMod80, // d8 d8+i fcomp st(i)
fRegSt + fMod80, // d8 e0+i fsub st(0), st(i)
fRegSt + fMod80, // d8 e8+i fsubr st(0), st(i)
fRegSt + fMod80, // d8 f0+i fdiv st(0), st(i)
fRegSt + fMod80)), // d8 f8+i fdivr st(0), st(i)
(opcode : $d9;
flags : (fNoReg + fMod32 + fPtr, // d9 /0 fld mdreal
fInvalid, // -----
fNoReg + fMod32 + fPtr, // d9 /2 fst mdreal
fNoReg + fMod32 + fPtr, // d9 /3 fstp mdreal
fNoReg + fMod8 + fPtr, // d9 /4 fldenv m14/28byte
fNoReg + fMod16 + fPtr, // d9 /5 fldcw m2byte
fNoReg + fMod8 + fPtr, // d9 /6 fnstenv m14/28byte
fNoReg + fMod16 + fPtr, // d9 /7 fnstcw m2byte
fNoReg + fMod80, // d9 c0+i fld st(i)
fNoReg + fMod80, // d9 c8+i fxch st(i)
fNoReg, // d9 d0 fnop
fNoReg + fMod80, // d9 d8+i fstp1 st(i)
fNoReg, // d9 e0 fxxx
fNoReg, // d9 e8 fxxx
fNoReg, // d9 f0 fxxx