8 Bit ALU for Computational Structures 1D. Based on Lucid with the Mojo v3 SPARTAN-6 FPGA.
Install the Mojo IDE and Xilinx ISE Design Suite, as described by the Mojo FPGA Beginner's Guide.
The main file for the mini hardware: calls the evaluator.luc and blinker.luc modules.
Manages the 3 full adder inputs A, B and C.
Takes the value of A,B and C, and returns a sum and carry.
A comparator receives another set of sum and carry from an IRL IC system, and determines their equality.
| Operation | ALUFN[5:0] |
|---|---|
| ADD | 000000 |
| SUB | 000001 |
| MUL | 000010 |
| DIV | 000011 |
| AND | 011000 |
| OR | 011110 |
| XOR | 010110 |
| "A" | 011010 |
| SHL | 100000 |
| SHR | 100001 |
| SRA | 100011 |
| CMPEQ | 110011 |
| CMPLT | 110101 |
| CMPLE | 110111 |